DSPIC30F5013-20E/PT Microchip Technology, DSPIC30F5013-20E/PT Datasheet - Page 89
DSPIC30F5013-20E/PT
Manufacturer Part Number
DSPIC30F5013-20E/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F5011-20IPT.pdf
(220 pages)
4.DSPIC30F5011-20IPT.pdf
(16 pages)
5.DSPIC30F5011-20IPT.pdf
(6 pages)
6.DSPIC30F5011-20IPT.pdf
(14 pages)
7.DSPIC30F5011-20IPT.pdf
(26 pages)
Specifications of DSPIC30F5013-20E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F5013-20EP
Available stocks
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Manufacturer
Quantity
Price
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- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20IP PDF datasheet #2
- DSPIC30F5011-20IPT PDF datasheet #3
- DSPIC30F5011-20IPT PDF datasheet #4
- DSPIC30F5011-20IPT PDF datasheet #5
- DSPIC30F5011-20IPT PDF datasheet #6
- DSPIC30F5011-20IPT PDF datasheet #7
- Current page: 89 of 220
- Download datasheet (4Mb)
14.3
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode with SSx pin
control enabled (SSEN = 1). When the SSx pin is low,
transmission and reception are enabled and the SDOx
pin is driven. When SSx pin goes high, the SDOx pin is
no longer driven. Also, the SPI module is re-
synchronized, and all counters/control circuitry are
reset. Therefore, when the SSx pin is asserted low
again, transmission/reception will begin at the MSb
even if SSx had been de-asserted in the middle of a
transmit/receive.
14.4
During Sleep mode, the SPI module is shutdown. If the
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by entering
or exiting Sleep mode.
© 2011 Microchip Technology Inc.
Slave Select Synchronization
SPI Operation During CPU Sleep
Mode
14.5
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
selects if the SPI module will stop or continue on Idle. If
SPISIDL = 0, the module will continue to operate when
the CPU enters Idle mode. If SPISIDL = 1, the module
will stop when the CPU enters Idle mode.
dsPIC30F5011/5013
SPI Operation During CPU Idle
Mode
DS70116J-page 89
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