PIC18F458T-I/PT Microchip Technology, PIC18F458T-I/PT Datasheet - Page 305

• Manufacturer Part Number: PIC18F458T-I/PT
• Description: IC MCU FLASH 16KX16 W/CAN 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F458T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
CNT
If CNT
PC
If CNT
PC
Q1
Q1
Q1
=
=
=
=
=
register ‘f’
operation
operation
operation
(f) + 1
The contents of register ‘f’ are
Increment f, Skip if 0
[ label ]
0
d
a
skip if result = 0
None
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0011
No
No
No
Q2
Q2
Q2
f
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
[0,1]
[0,1]
255
by a 2-word instruction.
dest,
INCFSZ
INCFSZ
:
:
11da
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
f [,d [,a]]
ffff
CNT
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
REG
If REG
PC
If REG
PC
Q1
Q1
Q1
=
=
=
=
=
register ‘f’
operation
operation
operation
Increment f, Skip if not 0
[ label ]
0
d
a
(f) + 1
skip if result
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
1
1(2)
Note:
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
f
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
[0,1]
[0,1]
PIC18FXX8
255
3 cycles if skip and followed
by a 2-word instruction.
dest,
INFSNZ
INFSNZ REG
10da
operation
operation
operation
Process
0
Data
No
No
No
Q3
Q3
Q3
DS41159E-page 303
f [,d [,a]]
ffff
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff