PIC16LF874A-I/L Microchip Technology, PIC16LF874A-I/L Datasheet - Page 127

• Manufacturer Part Number: PIC16LF874A-I/L
• Description: IC MCU FLASH 4KX14 EE A/D 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF874A-I/L

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Controller Family/series: PIC16LF
• No. Of I/o's: 33
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LF874A-I/LR; PIC16LF874A-I/LR; PIC16LF874AI/L

TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
10.4.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode. Bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR reg-
ister will transfer the data to the RCREG register and if
enable bit RCIE bit is set, the interrupt generated will
wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
 2003 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
19h
8Ch
98h
99h
Legend:
Note 1:
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note 1:
Address
Address
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear.
USART SYNCHRONOUS SLAVE
RECEPTION
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
INTCON
PIR1
RCSTA
TXREG
PIE1
TXSTA
SPBRG
Name
Name
USART Receive Register
Baud Rate Generator Register
PSPIF
PSPIE
USART Transmit Register
Baud Rate Generator Register
PSPIF
PSPIE
CSRC
SPEN
SPEN
CSRC
Bit 7
Bit 7
GIE
GIE
(1)
(1)
(1)
(1)
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
PEIE
ADIF
ADIE
Bit 6
RX9
TX9
TMR0IE
SREN
TXEN
TMR0IE
RCIE
RCIF
Bit 5
SREN
TXEN
RCIE
RCIF
Bit 5
CREN ADDEN
SYNC
INTE
Bit 4
TXIF
TXIE
CREN ADDEN
SYNC
INTE
Bit 4
TXIF
TXIE
SSPIF
SSPIE
RBIE
Bit 3
SSPIE
SSPIF
RBIE
Bit 3
—
—
When setting up a Synchronous Slave Reception,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
8.
9.
TMR0IF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
BRGH
TMR0IF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
FERR
Bit 2
BRGH
FERR
Bit 2
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
OERR
TRMT
OERR
INTF
TRMT
Bit 1
INTF
Bit 1
PIC16F87XA
RX9D
TX9D
RX9D
TX9D
Bit 0
R0IF
Bit 0
R0IF
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
0000 000x
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
0000 000x 0000 000u
POR, BOR
POR, BOR
Value on:
Value on:
DS39582B-page 125
0000 000u
Value on
Value on
all other
all other
Resets
Resets