AT90USB1287-MUR Atmel, AT90USB1287-MUR Datasheet - Page 318

• Manufacturer Part Number: AT90USB1287-MUR
• Description: MCU AVR 128K FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB1287-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90USBx
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.4.1
318
AT90USB64/128
Differential Channels
Figure 25-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 25-7. ADC Timing Diagram, Free Running Conversion
Table 25-1.
When using differential channels, certain aspects of the conversion need to be taken into
consideration.
Differential conversions are synchronized to the internal clock CK
clock frequency. This synchronization is done automatically by the ADC interface in such a way
that the sample-and-hold occurs at a specific phase of CK
user (i.e., all single conversions, and the first free running conversion) when CK
take the same amount of time as a single ended conversion (13 ADC clock cycles from the next
prescaled clock cycle). A conversion initiated by the user when CK
Condition
Sample & Hold
(Cycles from Start of Convertion)
Conversion Time
(Cycles)
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
ADC Conversion Time
Prescaler
Reset
MUX and REFS
Update
1
2
3
Sample &
Hold
4
Conversion
5
First
14.5
25
6
7
One Conversion
8
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
9
Conversion
Single Ended
10
Conversion,
Conversion
Complete
Complete
One Conversion
Normal
11
11
1.5
13
ADC2
12
12
13
13
. A conversion initiated by the
ADC2
Next Conversion
1
Sign and MSB of Result
Sign and MSB of Result
LSB of Result
ADC2
LSB of Result
2
Auto Triggered
MUX and REFS
Update
is high will take 14 ADC
Next Conversion
Convertion
equal to half the ADC
1
Prescaler
Reset
3
13.5
Sample & Hold
2
2
4
ADC2
7593K–AVR–11/09
is low will