AT90USB1287-MUR Atmel, AT90USB1287-MUR Datasheet - Page 35
![MCU AVR 128K FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90USB1287-MUR
Manufacturer Part Number
AT90USB1287-MUR
Description
MCU AVR 128K FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB646-MU.pdf
(461 pages)
Specifications of AT90USB1287-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
AT90USBx
Core
AVR8
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (5Mb)
5.5.7
7593K–AVR–11/09
External Memory Control Register B – XMCRB
Table 5-4.
• Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-
nal memory address space, see
• Bit 1..0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-
nal memory address space, see
Table 5-5.
Note:
• Bit 7– XMBK: External Memory Bus-keeper Enable
Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is
enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-
stated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE,
Bit
Read/Write
Initial Value
SRWn1
SRL2
0
0
1
1
0
0
0
1
1
1
1
1. n = 0 or 1 (lower/upper sector).
SRWn0
For further details of the timing and wait-states of the External Memory Interface, see Figures
5-6 through Figures 5-9 for how the setting of the SRW bits affects the timing.
7
XMBK
R/W
0
0
1
0
1
Sector limits with different settings of SRL2..0
Wait States
SRL1
0
1
1
0
0
1
1
R
6
–
0
Wait States
No wait-states
Wait one cycle during read/write strobe
Wait two cycles during read/write strobe
Wait two cycles during read/write and wait one cycle before driving out
new address
(1)
SRL0
5
–
R
0
x
0
1
0
1
0
1
Table
Table
4
–
R
0
Sector Limits
Lower sector = N/A
Upper sector = 0x2100 - 0xFFFF
Lower sector = 0x2100 - 0x3FFF
Upper sector = 0x4000 - 0xFFFF
Lower sector = 0x2100 - 0x5FFF
Upper sector = 0x6000 - 0xFFFF
Lower sector = 0x2100 - 0x7FFF
Upper sector = 0x8000 - 0xFFFF
Lower sector = 0x2100 - 0x9FFF
Upper sector = 0xA000 - 0xFFFF
Lower sector = 0x2100 - 0xBFFF
Upper sector = 0xC000 - 0xFFFF
Lower sector = 0x2100 - 0xDFFF
Upper sector = 0xE000 - 0xFFFF
5-5.
5-5.
3
–
R
0
2
XMM2
R/W
0
1
XMM1
R/W
0
AT90USB64/128
0
XMM0
R/W
0
XMCRB
35
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