ATMEGA1280V-8CUR Atmel, ATMEGA1280V-8CUR Datasheet - Page 290
ATMEGA1280V-8CUR
Manufacturer Part Number
ATMEGA1280V-8CUR
Description
MCU AVR 128K FLASH 8MHZ 100CBGA
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA1280V-8CUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
86
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Data Bus Width
8 bit
Data Ram Size
8 KB
Mounting Style
SMD/SMT
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK503 - STARTER KIT AVR EXP MODULE 100P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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25.8.2
2549M–AVR–09/10
ADCSRB – ADC Control and Status Register B
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a complete description of this bit, see
page
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
See
in effect until this conversion is complete (ADIF in ADCSRA is set).
• Bit 3 – MUX5: Analog Channel and Gain Selection Bit
This bit is used together with MUX4:0 in ADMUX to select which combination in of analog inputs
are connected to the ADC. See
the change will not go in effect until this conversion is complete.
This bit is not valid for ATmega1281/2561.
Table 25-4.
Bit
(0x7B)
Read/Write
Initial Value
000000
000001
000010
000011
000100
000101
000110
000111
MUX5:0
Table 25-4
294.
Input Channel Selections
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
Single Ended
for details. If these bits are changed during a conversion, the change will not go
R
7
–
0
Input
ACME
R/W
6
0
Table 25-4
ATmega640/1280/1281/2560/2561
Positive Differential
R
5
–
0
Input
for details. If this bit is changed during a conversion,
R
4
–
0
“ADCL and ADCH – The ADC Data Register” on
MUX5
R/W
3
0
ADTS2
Negative Differential
R/W
N/A
2
0
Input
ADTS1
R/W
1
0
ADTS0
R/W
0
0
ADCSRB
Gain
290
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