AT32UC3A0512-ALTTA Atmel, AT32UC3A0512-ALTTA Datasheet - Page 207
AT32UC3A0512-ALTTA
Manufacturer Part Number
AT32UC3A0512-ALTTA
Description
IC MCU AVR32 512K FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.ATEVK1104.pdf
(826 pages)
Specifications of AT32UC3A0512-ALTTA
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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23.8.1
Name:
Access Type:
•
0 = No effect.
1 = Enables the SPI to transfer and receive data.
•
0 = No effect.
1 = Disables the SPI.
As soon as SPDIS is set, SPI finishes its transfer.
All pins are set in input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the SPI is disabled.
If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.
•
0 = No effect.
1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.
The SPI is in slave mode after a software reset.
PDC channels are not affected by software reset.
•
0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this
allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD
transfer has completed.
32058J-AVR32-04/11
SPIEN: SPI Enable
SPIDIS: SPI Disable
SWRST: SPI Software Reset
LASTXFER: Last Transfer
SWRST
31
23
15
–
–
–
7
SPI Control Register
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
CR
Write-only
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
26
18
10
–
–
–
–
2
SPIDIS
25
17
–
–
–
9
1
AT32UC3A
LASTXFER
SPIEN
24
16
–
–
8
0
207
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