AT32UC3A0512-ALTTA Atmel, AT32UC3A0512-ALTTA Datasheet - Page 392

• Manufacturer Part Number: AT32UC3A0512-ALTTA
• Description: IC MCU AVR32 512K FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0512-ALTTA

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 27-26. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select.
27.6.7
27.6.7.1
32058J–AVR32–04/11
Write2 controlling
Read1 controlling
NBS0, NBS1,
signal(NWE)
signal(NRD)
CLK_SMC
A0, A1
A[25:2]
D[15:0]
External Wait
Restriction
TDF_CYCLES = 5
Any access can be extended by an external device using the NWAIT input signal of the SMC.
The EXNW_MODE field of the MODE register on the corresponding chip select must be set to
either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00” (dis-
abled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal
delays the read or write operation in regards to the read or write controlling signal, depending on
the read and write modes of the corresponding chip select.
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold
cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be
used in Page Mode
(”Slow Clock Mode” on page
The NWAIT signal is assumed to be a response of the external device to the read/write
request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the
read or write controlling signal. The assertion of the NWAIT signal outside the expected
period has no impact on SMC behavior.
Read1 cycle
Read1 hold = 1
Read to Write
(”Asynchronous Page Mode” on page
Wait State
TDF_CYCLES = 5
398).
4 TDF WAIT STATES
400), or in Slow Clock Mode
Write2 setup = 1
(optimization disabled)
TDF_MODE=0
Write 2 cycle
AT32UC3A
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