AT32UC3A0512-ALTTA Atmel, AT32UC3A0512-ALTTA Datasheet - Page 247

• Manufacturer Part Number: AT32UC3A0512-ALTTA
• Description: IC MCU AVR32 512K FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0512-ALTTA

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a
write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (THR).
• STOP: Send a STOP Condition
0 = No effect.
1 = STOP Condition is sent just after completing the current byte transmission in master read mode.
• MSEN: TWI Master Mode Enabled
0 = No effect.
1 = If MSDIS = 0, the master mode is enabled.
Note:
• MSDIS: TWI Master Mode Disabled
0 = No effect.
1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are
transmitted in case of write operation. In read operation, the character being transferred must be completely received
before disabling.
• SVEN: TWI Slave Mode Enabled
0 = No effect.
1 = If SVDIS = 0, the slave mode is enabled.
Note:
• SVDIS: TWI Slave Mode Disabled
0 = No effect.
1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read oper-
ation. In write operation, the character being transferred must be completely received before disabling.
• SWRST: Software Reset
0 = No effect.
1 = Equivalent to a system reset.
32058J-AVR32-04/11
- In single data byte master read, the START and STOP must both be set.
- In multiple data bytes master read, the STOP must be set after the last data received but one.
- In master read mode, if a NACK bit is received, the STOP is automatically performed.
- In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent.
Switching from Slave to Master mode is only permitted when TXCOMP = 1.
Switching from Master to Slave mode is only permitted when TXCOMP = 1.
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