ATMEGA64L-8AU Atmel, ATMEGA64L-8AU Datasheet - Page 144

• Manufacturer Part Number: ATMEGA64L-8AU
• Description: IC AVR MCU 64K 8MHZ 3V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64L-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 53
• Interface Type: JTAG/SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATmega
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5/5.8V
• Operating Supply Voltage (min): 2.4/2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer/Counter3,
Timer/Counter2
and
Timer/Counter1
Prescalers
Internal Clock Source
Prescaler Reset
External Clock Source
2490Q–AVR–06/10
Timer/Counter3, Timer/Counter2 and Timer/Counter1 share the same prescaler module, but the
Timer/Counters can have different prescaler settings. The description below applies to all of the
mentioned Timer/Counters.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, for example, it operates independently of the Clock Select logic of
the Timer/Counter, and it is shared by Timer/Counter1, Timer/Counter2, and Timer/Counter3.
Since the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler
will have implications for situations where a prescaled clock is used. One example of prescaling
artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The
number of system clock cycles from when the timer is enabled to the first count occurs can be
from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also use prescaling. A Prescaler Reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the Tn pin can be used as Timer/Counter clock
(clk
tion logic. The synchronized (sampled) signal is then passed through the edge detector.
59
logic. The registers are clocked at the positive edge of the internal system clock (
is transparent in the high period of the internal system clock.
The edge detector generates one clk
tive (CSn2:0 = 6) edge it detects.
Figure 59. Tn Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
CLK_I/O
shows a functional equivalent block diagram of the Tn synchronization and edge detector
T1
/clk
/1024.
clk
Tn
T2
I/O
/clk
T3
). The Tn pin is sampled once every system clock cycle by the pin synchroniza-
D Q
LE
CLK_I/O
). Alternatively, one of four taps from the prescaler can be used as a
D Q
T1
/clk
T
2
/clk
T
3
pulse for each positive (CSn2:0 = 7) or nega-
D
CLK_I/O
Q
Edge Detector
/8, f
ATmega64(L)
CLK_I/O
/64, f
clk
Tn_sync
(To Clock
Select Logic)
CLK_I/O
I/O
). The latch
/256, or
Figure
144