ATMEGA64L-8MU Atmel, ATMEGA64L-8MU Datasheet
ATMEGA64L-8MU
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ATMEGA64L-8MU Summary of contents
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... I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7V - 5.5V for Atmel ATmega64L – 4.5V - 5.5V for Atmel ATmega64 • Speed Grades – MHz for ATmega64L – MHz for ATmega64 ® ...
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Pin Configuration Figure 1. Pinout ATmega64 PEN RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (ICP3/INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6 Note: Disclaimer Typical ...
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Overview The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize ...
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... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega64 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega64 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits ...
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ATmega103 By programming the M103C Fuse, the ATmega64 will be compatible with the ATmega103 Compatibility Mode regards to RAM, I/O pins and Interrupt Vectors as described above. However, some new fea- tures in ATmega64 are not available in this compatibility ...
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Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins ...
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RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in 52. Shorter pulses are not guaranteed ...
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... Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 2490Q–AVR–06/10 1 ...
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About Code This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compi- Examples lation. Be aware that not all ...
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AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and ...
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Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between ...
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Status Register The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated ...
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Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose The Register File is optimized for the AVR Enhanced RISC ...
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X-, Y-, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are ...
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Figure 6 vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. ...
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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example sei sleep ; enter sleep, waiting for interrupt ; note: will enter ...
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AVR Memories This section describes the different memories in the ATmega64. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega64 features an EEPROM Memory for data storage. All three ...
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SRAM Data The ATmega64 supports two different configurations for the SRAM data memory as listed in Memory Table 1. Table 1. Memory Configurations Configuration Normal mode ATmega103 compatibility mode Figure 9 The ATmega64 is a complex microcontroller with more peripheral ...
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The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented ...
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Data Memory Access This section describes the general access timing concepts for internal memory access. The Times internal data SRAM access is performed in two clk Figure 10. On-chip Data SRAM Access Cycles EEPROM Data The ATmega64 contains 2 Kbytes ...
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EEARH and EEARL – Bit EEPROM Address 0x1F (0x3F) Register 0x1E (0x3E) Read/Write Initial Value • Bits 15..11 – Res: Reserved Bits These are reserved bits and will always read as zero. When writing to this address location, write these ...
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Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within four clock cycles will write ...
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Table 2. EEPROM Programming Time Symbol EEPROM write (from CPU) Note: The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example, by disabling inter- rupts ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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Preventing EEPROM During periods of low V Corruption too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An ...
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External Memory With all the features that the External Memory Interface provides well suited to operate as Interface an interface to memory devices such as external SRAM and Flash, and peripherals such as LCD-display, A/D, and D/A. The ...
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ATmega103 Both External Memory Control Registers, XMCRA and XMCRB, are placed in Extended I/O Compatibility space. In ATmega103 compatibility mode, these registers are not available, and the features selected by these registers are not available. The device is still ATmega103 ...
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Figure 12. External SRAM Connected to the AVR Pull-up and Bus The pull-ups on the AD7:0 ports may be activated if the corresponding Port Register is written to Keeper one. To reduce power consumption in sleep mode recommended ...
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Figure 13. External Data Memory Cycles without Wait State (SRWn1 = 0 and SRWn0 =0) System Clock (CLK Note: Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1 System Clock (CLK Note: 2490Q–AVR–06/ ...
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Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0 System Clock (CLK Note: Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1 System Clock (CLK Note: 2490Q–AVR–06/ ...
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XMEM Register Description MCUCR – MCU Bit Control Register 0x35 (0x55) Read/Write Initial Value • Bit 7 – SRE: External SRAM/XMEM Enable Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are ...
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Table 3. Sector Limits with Different Settings of SRL2..0 SRL2 • Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait State Select Bits for Upper Sector The SRW11 and SRW10 bits ...
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XMCRB – External Bit Memory Control (0x6C) Register B Read/Write Initial Value • Bit 7 – XMBK: External Memory Bus Keeper Enable Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper is enabled, ...
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Using all Locations of Since the external memory is mapped after the internal memory as shown in External Memory external memory is not addressed when addressing the first 4,352 bytes of data space. It may Smaller than 64 appear that ...
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Using all 64Kbytes Since the external memory is mapped after the internal memory as shown in Locations of External Kbytes of external memory is available by default (address space 0x0000 to 0x10FF is reserved Memory for internal memory). However, it ...
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System Clock and Clock Options Clock Systems Figure 18 need not be active at a given time. In order to reduce power consumption, the clocks to modules and their not being used can be halted by using different sleep modes, ...
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Asynchronous Timer The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly Clock – clk from an external 32 kHz clock crystal. The dedicated clock domain allows using this ASY Timer/Counter as a real-time counter even when the ...
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XDIV – XTAL Divide The XTAL Divide Control Register is used to divide the source clock frequency by a number in Control Register the range 2 - 129. This feature can be used to decrease power consumption when the require- ...
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Figure 19. Crystal Oscillator Connections The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8. Crystal Oscillator Operating Modes CKOPT 1 ...
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Table 9. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 Notes: Low-frequency To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency crystal Crystal Oscillator ...
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External RC For timing insensitive applications, the external RC configuration shown in Oscillator used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT Fuse, the user can ...
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... RC Oscillator. At 5V, 25°C and 1.0 MHz Oscillator fre- quency selected, this calibration gives a frequency within ±3% of the nominal frequency. Using run-time calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ±1% accuracy at any given V used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out ...
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Oscillator. Writing 0xFF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, ...
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Timer/Counter For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is Oscillator connected directly between the pins. No external capacitors are needed. The Oscillator is opti- mized for use with a 32.768 kHz watch crystal. Applying an ...
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Power Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- Management tion to the application’s requirements. and Sleep To ...
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Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue ...
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Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. ...
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Minimizing Power There are several issues to consider when trying to minimize the power consumption in an AVR Consumption controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so ...
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JTAG Interface and If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or On-chip Debug Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will System ...
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System Control and Reset Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – absolute ...
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Figure 22. Reset Logic BODLEVEL Table 19. Reset Characteristics Symbol V POT V RST t RST V BOT t BOD V HYST Notes: 2490Q–AVR–06/ PEN L Q Pull-up Resistor Power-On Reset Circuit BODEN Reset Circuit Pull-up Resistor SPIKE ...
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... V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1 for ATmega64L and BODLEVEL=0 for ATmega64. BODLEVEL=1 is not appli- cable for ATmega64. Table 19. The POR is activated whenever V rise ...
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External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset ...
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Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t page 56 Figure 27. Watchdog ...
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Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a ...
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Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON M103C Unprogrammed Unprogrammed Programmed Programmed Figure 28. Watchdog Timer WDTCR – Watchdog Bit Timer Control Register 0x21 (0x41) Read/Write Initial Value • Bits 7..5 – ...
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To disable an enabled Watchdog Timer, the following procedure must be followed the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it ...
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The following code examples show one assembly and one C function for turning off the WDT. The examples assume that interrupts are controlled (for example, by disabling interrupts glob- ally) so that no interrupts will occur during execution of these ...
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Timed Sequences The sequence for changing configuration differs slightly between the three safety levels. Sepa- for Changing the rate procedures are described for each level. Configuration of the Watchdog Timer Safety Level 0 This mode is compatible with the Watchdog ...
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Interrupts This section describes the specifics of the interrupt handling as performed in ATmega64. For a general explanation of the AVR interrupt handling, refer to page 15. Interrupt Vectors Table 23. Reset and Interrupt Vectors in ATmega64 Vector No. 1 ...
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Table 23. Reset and Interrupt Vectors (Continued) Vector No Notes: Table 24 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be ...
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RESET: ldi 0x0047 0x0048 0x0049 0x004A 0x004B ... When the BOOTRST Fuse is unprogrammed, the Boot section size set to ...
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When the BOOTRST Fuse is programmed and the Boot section size set to 8 Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code .org 0x0002 0x0002 0x0004 ... 0x0044 ; ...
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Loader section of the Flash. The actual address of the start of the Boot Flash section is deter- mined by the BOOTSZ Fuses. Refer to the section Self-programming” on page 277 tables, a special write procedure must be followed to ...
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I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the ...
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Figure 30. General Digital I/O Pxn Note: Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in Description for I/O Ports” on page PORTxn bits at the PORTx I/O address, and the ...
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When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state ...
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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...
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The following code example show how to set Port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...
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Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin enable ...
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Table 26. Generic Description of Overriding Signals for Alternate Functions Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the ...
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Alternate Functions of The Port A has an alternate function as the address low byte and data lines for the External Port A Memory Interface. Table 27. Port A Pins Alternate Functions Port Pin PA7 PA6 PA5 PA4 PA3 PA2 ...
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Table 29. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: Alternate Functions of The Port B pins with alternate functions are shown in Port B Table 30. Port ...
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OC1B, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this ...
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Table 31. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: Table 32. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE ...
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Alternate Functions of In ATmega103 compatibility mode, Port C is output only. The Port C has an alternate function as Port C the address high byte for the External Memory Interface Table 33. Port C Pins Alternate Functions Table 34 ...
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Table 35. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: Alternate Functions of The Port D pins with alternate functions are shown in Port D Table 36. Port ...
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INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt Source 3: The PD3 pin can serve as an External Interrupt source to the MCU. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 transmitter is enabled, ...
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Table 37. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 38. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI ...
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Alternate Functions of The Port E pins with alternate functions are shown in Port E Table 39. Port E Pins Alternate Functions Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Note: • INT7/ICP3 – Port E, Bit 7 ...
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AIN0/XCK0 – Port E, Bit 2 AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. XCK0, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is ...
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Table 41. Overriding Signals for Alternate Functions in PE3..PE0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Alternate Functions of The Port F has an alternate function as analog input for the ADC as shown in ...
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TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5 TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can ...
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Table 44. Overriding Signals for Alternate Functions in PF3..PF0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Alternate Functions of In ATmega103 compatibility mode, only the alternate functions are the defaults for Port G, and Port ...
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WR – Port G, Bit the external data memory write control strobe. Table 46 Figure 33 on page Table 46. Overriding Signals for Alternate Functions in PG4..PG1 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE ...
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Register Description for I/O Ports PORTA – Port A Data Bit Register 0x1B (0x3B) Read/Write Initial Value DDRA – Port A Data Bit Direction Register 0x1A (0x3A) Read/Write Initial Value PINA – Port A Input Bit Pins Address 0x19 (0x39) ...
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PINC – Port C Input Bit Pins Address 0x13 (0x33) Read/Write Initial Value In ATmega103 compatibility mode, DDRC and PINC Registers are initialized to being Push-pull Zero Output. The port pins assumes their Initial Value, even if the clock is ...
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DDRF – Port F Data Bit Direction Register (0x61) Read/Write Initial Value PINF – Port F Input Bit Pins Address 0x00 (0x20) Read/Write Initial Value Note that PORTF and DDRF Registers are not available in ATmega103 compatibility mode where Port ...
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External The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of gen- Interrupts erating a software interrupt. The ...
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Table 48. Interrupt Sense Control ISCn1 Note: Table 49. Asynchronous External Interrupt Characteristics Symbol t INT EICRB – External Bit Interrupt Control 0x3A (0x5A) Register B Read/Write Initial Value • Bits 7..0 – ISC71, ISC70 - ...
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EIMSK – External Bit Interrupt Mask 0x39 (0x59) Register Read/Write Initial Value • Bits 7..4 – INT7 - INT0: External Interrupt Request Enable When an INT7 - INT4 bit is written to one and the I-bit in ...
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Timer/Counter0 is a general purpose, single-channel, 8-bit Timer/Counter module. The main features are: Timer/Counter0 • Single Channel Counter with PWM and • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) Asynchronous • ...
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The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result ...
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Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 35 shows a block diagram of the counter and its surrounding environment. Figure 35. Counter Unit Block Diagram Signal description (internal signals): count direction clear ...
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Figure 36. Output Compare Unit, Block Diagram The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff- ering is ...
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Compare Match The Compare Output mode (COM01:0) bits have two functions. The Waveform Generator uses Output Unit the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match. Also, the COM01:0 bits control the OC0 pin ...
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Modes of The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, Operation is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Out- put mode (COM01:0) bits. The Compare Output ...
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TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in ...
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Figure 39. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the ...
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Phase Correct PWM The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM Mode waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to ...
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The PWM frequency for the output when using phase correct PWM can be calculated by the fol- lowing equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR0 ...
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Figure 42. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 43 Figure 43. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk clk (clk TCNTn OCRn OCFn Figure 44 Figure 44. Timer/Counter Timing Diagram, Clear ...
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Timer/Counter Register Description TCCR0 – Bit Timer/Counter Control 0x33 (0x53) Register Read/Write Initial Value • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM bits specify a non-PWM mode. However, for ensur- ...
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Table 53. Compare Output Mode, non-PWM Mode COM01 Table 54 mode. Table 54. Compare Output Mode, Fast PWM Mode COM01 Note: Table 55 PWM mode. Table 55. Compare Output Mode, Phase Correct ...
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Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 56. Table 56. Clock Select Bit Description CS02 TCNT0 ...
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Asynchronous Operation of the Timer/Counter ASSR – Asynchronous Bit Status Register 0x30 (0x50) Read/Write Initial Value • Bit 3 – AS0: Asynchronous Timer/Counter0 When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clk written to one, ...
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The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter0 operation. The CPU main clock frequency must be more than four times the Oscillator ...
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Write any value to either of the registers OCR0 or TCCR0. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT0. • During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer ...
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Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard- ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a ...
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SFIOR – Special Bit Function IO Register 0x20 (0x40) Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to PSR0 ...
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The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: Timer/Counter • True 16-bit Design (that is, allows 16-bit PWM) (Timer/Counter • Three Independent Output Compare Units • ...
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Figure 46. 16-bit Timer/Counter Block Diagram Note: Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg- ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described ...
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See “Output Compare Units” on page 121. Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either ...
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Accessing 16-bit The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU Registers via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write opera- tions. Each 16-bit ...
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The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: C Code Example unsigned ...
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The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: C Code Example void ...
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Figure 47. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk T n TOP BOTTOM The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con- taining the upper eight bits of the ...
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Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul- tiple events, can be applied via the ICPn ...
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Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL. For more information on how to access the 16-bit registers refer to on page Input ...
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Output Compare The 16-bit comparator continuously compares TCNTn with the Output Compare Register Units (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle. If ...
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TCNTn – and ICRn Register). Therefore OCRnx is not read via the high byte temporary register (TEMP). However good practice to read the low byte first as when accessing other 16-bit registers. Writing the ...
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Figure 50. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx clk The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction ...
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Modes of The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, Operation is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Out- put mode (COMnx1:0) bits. The Compare Output ...
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An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according to the register used to define the TOP value. If the inter- rupt is enabled, the ...
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Figure 52. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn flag is set at the same timer clock cycle as ...
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The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM ...
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Figure 53. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ...
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The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set ...
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Figure 54. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM). ...
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TOP the output will be set to high for non- inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCnA is used to define ...
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Figure 57. Timer/Counter Timing Diagram, no Prescaling (CTC and FPWM) (PC and PFC PWM) TOVn and ICFn (Update at TOP) Figure 58 Figure 58. Timer/Counter Timing Diagram, with Prescaler (f (CTC and FPWM) (PC and PFC PWM) and ICFn (Update ...
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Initial Value • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B • Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C The COMnA1:0, COMnB1:0, and COMnC1:0 ...
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Table 58. Compare Output Mode, non-PWM COMnA1/ COMnB1/ COMnC1 Table 59 mode Table 59. Compare Output Mode, Fast PWM COMnA1/ COMnB1/ COMnC0 Note: Table 59 rect and frequency correct PWM mode. 2490Q–AVR–06/10 ...
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Table 60. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM COMnA1/ COMnB1/ COMnC1 Note: • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these ...
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Table 61. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...
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Bit 6 – ICESn: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge ...
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TCCR3C – Bit Timer/Counter3 (0x8C) Control Register C Read/Write Initial Value • Bit 7 – FOCnA: Force Output Compare for Channel A • Bit 6 – FOCnB: Force Output Compare for Channel B • Bit 5 – FOCnC: Force Output ...
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OCR1AH and OCR1AL Bit –Output Compare 0x2B (0x4B) Register 1 A 0x2A (0x4A) Read/Write Initial Value OCR1BH and OCR1BL Bit – Output Compare 0x29 (0x49) Register 1 B 0x28 (0x48) Read/Write Initial Value OCR1CH and OCR1CL Bit – Output Compare ...
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ICR1H and ICR1L – Bit Input Capture Register 0x27 (0x47) 1 0x26 (0x46) Read/Write Initial Value ICR3H and ICR3L – Bit Input Capture Register 3 (0x81) (0x80) Read/Write Initial Value The Input Capture is updated with the counter (TCNTn) value ...
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Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” ...
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TIFR – Timer/Counter Bit Interrupt Flag 0x36 (0x56) (1) Register Read/Write Initial Value Note: • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture ...
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Bit 5 – ICF3: Timer/Counter3, Input Capture Flag This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register (ICR3) is set by the WGM3 used as the TOP value, ...
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Timer/Counter3, Timer/Counter3, Timer/Counter2 and Timer/Counter1 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all of the Timer/Counter2 mentioned Timer/Counters. and Timer/Counter1 Prescalers Internal Clock Source The Timer/Counter can be clocked ...
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However, due to variation of the system clock frequency and duty cycle caused by Oscillator source ...
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Timer/Counter2 is a general purpose, single-channel, 8-bit Timer/Counter module. The main features are: Timer/Counter2 • Single Channel Counter with PWM • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse width Modulator (PWM) • Frequency Generator ...
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PWM or variable frequency output on the Output Compare pin (OC2). For details, see “Output Compare Unit” on page 148. The Compare Match event will also set the Compare Flag (OCF2) which can be used to generate an ...
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Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 62 shows a block diagram of the counter and its surroundings. Figure 62. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk ...
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Figure 63. Output Compare Unit, Block Diagram The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff- ering is ...
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Using the Output Since writing TCNT2 in any mode of operation will block all Compare Matches for one timer Compare Unit clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the ...
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OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic ...
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Figure 65. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 flag. If the interrupt is enabled, the interrupt handler routine can be ...
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Figure 66. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the ...
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In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmet- ric feature of the dual-slope PWM modes, these modes are preferred for motor ...
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The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2 is set ...
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Figure 69. Timer/Counter Timing Diagram, with Prescaler (f (clk TCNTn Figure 70 Figure 70. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk clk (clk TCNTn OCRn OCFn Figure 71 2490Q–AVR–06/10 clk I/O clk Tn /8) I/O MAX - ...
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Figure 71. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O clk clk (clk TCNTn (CTC) OCRn OCFn 8-bit Timer/Counter Register Description TCCR2 – Bit Timer/Counter Control 0x25 (0x45) Register Read/Write Initial Value • Bit ...
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Table 64. Waveform Generation Mode Bit Description Mode Note: • Bit 5:4 – COM21:0: Compare Match Output Mode These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits are ...
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Table 67. Compare Output Mode, Phase Correct PWM Mode COM21 Note: • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 68. Clock ...
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OCR2 – Output Bit Compare Register 0x23 (0x43) Read/Write Initial Value The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or ...
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Output Compare Modulator (OCM1C2) Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of ...
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Figure 73. Output Compare Modulator, Schematic COM21 COM20 COM1C1 COM1C0 ( From Waveform Generator ) ( From Waveform Generator ) When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. ...
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SPI – Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega64 and peripheral devices or between several AVR devices. The ATmega64 SPI Peripheral includes the following features: Interface • Full-duplex, Three-wire Synchronous Data Transfer • ...
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Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may ...
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The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 2490Q–AVR–06/10 (1) ; ...
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SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the ...
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Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, ...
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SPSR – SPI Status Bit Register 0x0E (0x2E) Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set ...
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Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in 77 and ensuring sufficient time for data ...
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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or ...
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The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation logic consists of synchronization logic for ...
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Figure 80. Clock Generation Logic, Block Diagram Signal description: txclk rxclk xcki xcko fosc Internal Clock Internal clock generation is used for the asynchronous and the synchronous master modes of Generation – The operation. The description in this section refers ...
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Table 74. Equations for Calculating Baud Rate Register Setting Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD Baud rate (in bits per second, bps) f OSC UBRR Contents ...
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Figure 81. Synchronous Mode XCK Timing The UCPOLn bit UCRSnC selects which XCK clock edge is used for data sampling and which is used for data change. As rising XCK edge and sampled at falling XCK edge. If UCPOLn is ...
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Receiver and Transmitter. The USART Character Size (UCSZn2:0) bits select the number of data bits in the frame. The USART Parity mode (UPMn1:0) bits enable ...
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Assembly Code Example USART_Init: C Code Example #define FOSC 1843200// Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ) { } void USART_Init( unsigned int ubrr ) { } Note: More advanced initialization routines can be made ...
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Data Transmission The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB – The USART Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid- den by the USART ...
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Sending Frames with If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8n bit in 9 Data Bits UCSRnB before the low byte of the character is written to UDRn. The following code ...
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Transmitter Flags and The USART Transmitter has two flags that indicate its state: USART Data Register Empty Interrupts (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) flag indicates whether the ...
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Data Reception – The USART Receiver is enabled by writing the Receive Enable n (RXENn) bit in the UCSRnB The USART Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is over- ridden ...
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Receiving Frames with If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in 9 Data Bits UCSRnB before reading the low bits from the UDR. This rule applies to the FEn, DORn, and ...
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The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early ...
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Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the receiver will no longer override the ...
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The Clock Recovery logic then uses samples 8, 9 and 10 for Normal mode, and sam- ples 4, 5 and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a ...
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Asynchronous The operational range of the Receiver is dependent on the mismatch between the received bit Operational Range rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or ...
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Table 75. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) # (Data+Parity Bit) Table 76. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = 1) # (Data+Parity Bit) The recommendations of the ...
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If a particular Slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. Using MPCM For an MCU to ...
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Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the TxD pin. The receive buffer consists of a two level FIFO. The FIFO will change its state ...
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Bit 1 – U2Xn: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the ...
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Bit 1 – RXB8n: Receive Data Bit 8 RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDRn. • Bit ...
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Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 79. USBS Bit Settings • Bit 2:1 – UCSZn1:0: Character Size The ...
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UBRRnL and UBRRnH Bit – USART Baud Rate (1) Registers Read/Write Initial Value Note: • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when ...
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Table 82. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2X = 0 Rate (bps) UBRRn Error UBRRn 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 -7.0% 12 14.4k 3 8.5% ...
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Table 83. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
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Table 84. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRRn Error UBRRn 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
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Table 85. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRRn Error UBRRn 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...
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TWI – Two-wire Serial Interface Features • Simple yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space allows up ...
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Electrical As depicted in Interconnection pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line ...
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Figure 88. START, REPEATED START, and STOP Conditions SDA SCL Address Packet All address packets transmitted on the TWI bus are nine bits long, consisting of seven address Format bits, one READ/WRITE control bit and an acknowledge bit. If the ...