PIC18LF8621-I/PT Microchip Technology, PIC18LF8621-I/PT Datasheet - Page 30

• Manufacturer Part Number: PIC18LF8621-I/PT
• Description: IC PIC MCU FLASH 32KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8621-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3840Byte
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 2 x 8 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F6525/6621/8525/8621
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram, indi-
cating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-12.
FIGURE 2-12:
2.7
When the device executes a SLEEP instruction, the on-
chip clocks and oscillator are turned off and the device
is held at the beginning of an instruction cycle (Q1
state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
TABLE 2-3:
2.8
Power-up delays are controlled by two timers so that no
external
applications. The delays ensure that the device is kept
in Reset until the device power supply and clock are
stable. For additional information on Reset operation,
see Section 3.0 “Reset”.
The first timer is the Power-up Timer (PWRT) which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer (OST), intended to keep
the chip in Reset until the crystal oscillator is stable.
DS39612B-page 28
RC
RCIO
ECIO
EC
LP, XT and HS
Oscillator Mode
Note:
Note:
Internal System
(OSCCON<0>)
Program
Counter
Effects of Sleep Mode on the
On-Chip Oscillator
Power-up Delays
RC Oscillator mode assumed.
T1OSI
OSC1
Clock
Reset
SCS
See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset.
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
circuitry
Q3
Floating, external resistor should pull high
Floating, external resistor should pull high
Floating
Floating
Feedback inverter disabled at
quiescent voltage level
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
is
PC
required
Q4
OSC1 Pin
for
most
Q1
T
1
OSC
T
switching currents have been removed, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during Sleep will increase the current
consumed during Sleep. The user can wake from
Sleep through external Reset, Watchdog Timer Reset,
or through an interrupt.
With the PLL enabled (HS+PLL and EC+PLL oscillator
mode), the time-out sequence following a Power-on
Reset is different from other oscillator modes. The
time-out sequence is as follows: First, the PWRT time-
out is invoked after a POR time delay has expired.
Then, the Oscillator Start-up Timer (OST) is invoked.
However, this is still not a sufficient amount of time to
allow the PLL to lock at high frequencies. The PWRT
timer is used to provide an additional fixed 2 ms
(nominal) time-out to allow the PLL ample time to lock
to the incoming clock frequency.
T
2
1
P
At logic low
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low
Feedback inverter disabled at
quiescent voltage level
3
PC + 2
4
T
SCS
5
6
7
8
 2005 Microchip Technology Inc.
OSC2 Pin
Q1 Q2 Q3 Q4 Q1 Q2 Q3
PC + 4
Q4