AT90USB1287-MU Atmel, AT90USB1287-MU Datasheet - Page 160

IC AVR MCU 128K 64QFN

AT90USB1287-MU

Manufacturer Part Number
AT90USB1287-MU
Description
IC AVR MCU 128K 64QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet

Specifications of AT90USB1287-MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64QFN EP
Device Core
AVR
Family Name
AT90
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT90USB1287-16MU
AT90USB1287-16MU

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90USB1287-MU
Manufacturer:
KEMET
Quantity:
30 000
Part Number:
AT90USB1287-MU
Manufacturer:
ATMEL
Quantity:
3 335
15.8
15.8.1
160
8-bit Timer/Counter Register Description
AT90USB64/128
Timer/Counter Control Register A – TCCR2A
Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
• Bits 7:6 – COM2A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin
must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting.
are set to a normal or CTC mode (non-PWM).
Table 15-1.
Bit
Read/Write
Initial Value
COM2A1
0
0
1
1
TCNTn
(clk
OCRnx
(CTC)
OCFnx
clk
clk
I/O
I/O
Tn
/8)
7
COM2A
1
R/W
0
caler (f
Compare Output Mode, non-PWM Mode
COM2A0
0
1
0
1
clk_I/O
Table 15-1
6
COM2A
0
R/W
0
TOP - 1
/8)
Description
Normal port operation, OC2A disconnected.
Toggle OC2A on Compare Match
Clear OC2A on Compare Match
Set OC2A on Compare Match
5
COM2B
1
R/W
0
shows the COM2A1:0 bit functionality when the WGM22:0 bits
4
COM2B
0
R/W
0
TOP
3
R
0
TOP
2
R
0
BOTTOM
1
WGM2
1
R/W
0
0
WGM2
0
R/W
0
BOTTOM + 1
TCCR2A
7593K–AVR–11/09

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