AT90USB1287-MU Atmel, AT90USB1287-MU Datasheet - Page 244
![IC AVR MCU 128K 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90USB1287-MU
Manufacturer Part Number
AT90USB1287-MU
Description
IC AVR MCU 128K 64QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB646-MU.pdf
(461 pages)
Specifications of AT90USB1287-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64QFN EP
Device Core
AVR
Family Name
AT90
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT90USB1287-16MU
AT90USB1287-16MU
AT90USB1287-16MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90USB1287-MU
Manufacturer:
KEMET
Quantity:
30 000
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20.9
244
Multi-master Systems and Arbitration
AT90USB64/128
If multiple masters are connected to the same bus, transmissions may be initiated simultane-
ously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the masters will be allowed to proceed with the transfer, and that no data
will be lost in the process. An example of an arbitration situation is depicted below, where two
masters are trying to transmit data to a Slave Receiver.
Figure 20-21. An Arbitration Example
Several different scenarios may arise during arbitration, as described below:
This is summarized in
• Two or more masters are performing identical communication with the same Slave. In this
• Two or more masters are accessing the same Slave with different data or direction bit. In this
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
case, neither the Slave nor any of the masters will know about the bus contention.
case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters
trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
Losing masters will switch to not addressed Slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
SDA
SCL
TRANSMITTER
Device 1
MASTER
Figure
20-22. Possible status values are given in circles.
TRANSMITTER
Device 2
MASTER
Device 3
RECEIVER
SLAVE
........
Device n
V
CC
R1
R2
7593K–AVR–11/09
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