AT90USB1287-MU Atmel, AT90USB1287-MU Datasheet - Page 294

IC AVR MCU 128K 64QFN

AT90USB1287-MU

Manufacturer Part Number
AT90USB1287-MU
Description
IC AVR MCU 128K 64QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet

Specifications of AT90USB1287-MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64QFN EP
Device Core
AVR
Family Name
AT90
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT90USB1287-16MU
AT90USB1287-16MU

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90USB1287-MU
Manufacturer:
KEMET
Quantity:
30 000
Part Number:
AT90USB1287-MU
Manufacturer:
ATMEL
Quantity:
3 335
23.12 Control Pipe management
23.13 OUT Pipe management
294
AT90USB64/128
A Control transaction is composed of 3 phases:
The firmware has to change the Token for each phase.
The initial data toggle is set for the corresponding token (ONLY for Control Pipe):
The Pipe must be configured and not frozen first.
Note: if the firmware decides to switch to suspend mode (clear SOFEN) even if a bank is ready
to be sent, the USB controller will automatically exit from Suspend mode and the bank will be
sent.
The TXOUT bit is set by hardware when the current bank becomes free. This triggers an inter-
rupt if the TXOUTE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the
FIFO and clears the FIFOCON bit to allow the USB controller to send the data.
• SETUP
• Data (IN or OUT)
• Status (OUT or IN)
• SETUP: Data0
• OUT: Data1
• IN: Data1 (expected data toggle)
7593K–AVR–11/09

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