ATSAM3U4CA-AU Atmel, ATSAM3U4CA-AU Datasheet - Page 116
![IC MCU 32BIT 256KB FLASH 100LQFP](/photos/6/76/67646/313-100-lqfp_sml.jpg)
ATSAM3U4CA-AU
Manufacturer Part Number
ATSAM3U4CA-AU
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U4CA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
57
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
52K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b, 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
52 KB
Interface Type
3xUSART, TWI, 4xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
57
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Controller Family/series
SAM3U
No. Of I/o's
57
Ram Memory Size
52KB
Cpu Speed
96MHz
No. Of Timers
3
Rohs Compliant
Yes
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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13.11.8
13.11.8.1
13.11.8.2
13.11.8.3
116
SAM3U Series
LDREX and STREX
Syntax
Operation
Restrictions
Load and Store Register Exclusive.
where:
cond
Rd
Rt
Rn
offset
LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory
address.
STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a
memory address. The address used in any Store-Exclusive instruction must be the same as the
address in the most recently executed Load-exclusive instruction. The value stored by the Store-
Exclusive instruction must also have the same data size as the value loaded by the preceding
Load-exclusive instruction. This means software must always use a Load-exclusive instruction
and a matching Store-Exclusive instruction to perform a synchronization operation, see
chronization primitives” on page 77
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does
not perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction
writes 0 to the destination register, it is guaranteed that no other process in the system has
accessed the memory location between the Load-exclusive and Store-Exclusive instructions.
For reasons of performance, keep the number of instructions between corresponding Load-
Exclusive and Store-Exclusive instruction to a minimum.
The result of executing a Store-Exclusive instruction to an address that is different from that
used in the preceding Load-Exclusive instruction is unpredictable.
In these instructions:
• do not use PC
• do not use SP for Rd and Rt
• for STREX, Rd must be different from both Rt and Rn
• the value of offset must be a multiple of four in the range 0-1020.
LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
is an optional condition code, see
is the destination register for the returned status.
is the register to load or store.
is the register on which the memory address is based.
is an optional offset applied to the value in Rn.
If offset is omitted, the address is the value in Rn.
“Conditional execution” on page
6430D–ATARM–25-Mar-11
100.
“Syn-
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