ATSAM3U4CA-AU Atmel, ATSAM3U4CA-AU Datasheet - Page 714
![IC MCU 32BIT 256KB FLASH 100LQFP](/photos/6/76/67646/313-100-lqfp_sml.jpg)
ATSAM3U4CA-AU
Manufacturer Part Number
ATSAM3U4CA-AU
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U4CA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
57
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
52K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b, 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
52 KB
Interface Type
3xUSART, TWI, 4xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
57
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Controller Family/series
SAM3U
No. Of I/o's
57
Ram Memory Size
52KB
Cpu Speed
96MHz
No. Of Timers
3
Rohs Compliant
Yes
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Figure 35-31. T = 0 Protocol with Parity Error
35.7.4.3
714
714
Receive Error Counter
Receive NACK Inhibit
Transmit Character Repetition
Disable Successive Receive NACK
Baud Rate
Clock
I/O
SAM3U Series
SAM3U Series
Protocol T = 1
Start
Bit
D0
The USART receiver also records the total number of errors. This can be read in the Number of
Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER
automatically clears the NB_ERRORS field.
The USART can also be configured to inhibit an error. This can be achieved by setting the
INACK bit in the Mode Register (US_MR). If INACK is to 1, no error signal is driven on the I/O
line even if a parity bit is detected.
Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding
Register, as if no error occurred and the RXRDY bit does rise.
When the USART is transmitting a character and gets a NACK, it can automatically repeat the
character before moving on to the next one. Repetition is enabled by writing the
MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character
can be transmitted up to eight times; the first transmission plus seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as
the value loaded in MAX_ITERATION.
When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the
Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the
receiver, the repetitions are stopped and the iteration counter is cleared.
The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit
to 1.
The receiver can limit the number of successive NACKs sent back to the remote transmitter.
This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum
number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as
MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on
the line and the ITERATION bit in the Channel Status Register is set.
When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous for-
mat with only one stop bit. The parity is generated when transmitting and checked when
receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR).
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Time 1
Guard
Error
Time 2
Guard
Start
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Bit
Repetition
D0
D1
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