ATSAM3U4CA-AU Atmel, ATSAM3U4CA-AU Datasheet - Page 373
ATSAM3U4CA-AU
Manufacturer Part Number
ATSAM3U4CA-AU
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U4CA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
57
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
52K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b, 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
52 KB
Interface Type
3xUSART, TWI, 4xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
57
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Controller Family/series
SAM3U
No. Of I/o's
57
Ram Memory Size
52KB
Cpu Speed
96MHz
No. Of Timers
3
Rohs Compliant
Yes
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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Manufacturer
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Figure 25-19. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins
25.13.3
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
D[15:0]
A [23:2]
NCS0
NWE
MCK
NRD
TDF Optimization Disabled (TDF_MODE = 0)
read access on NCS0 (NRD controlled)
When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that
the data float period ends when the second access begins. If the hold period of the read1 con-
trolling signal overlaps the data float period, no additional tdf wait states will be inserted.
Figure
with no TDF optimization.
• read access followed by a read access on another chip select,
• read access followed by a write access on another chip select,
• read access followed by a write access on the same chip select,
25-20,
Figure 25-21
NRD_HOLD= 4
TDF_CYCLES = 6
and
Figure 25-22
Read to Write
Wait State
NWE_SETUP= 3
illustrate the cases:
write access on NCS0 (NWE controlled)
SAM3U Series
SAM3U Series
373
373
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