ATSAM3U2EA-CU Atmel, ATSAM3U2EA-CU Datasheet - Page 32
![IC MCU 32BIT 128KB FLSH 144LFBGA](/photos/12/13/121356/144-lfbga_sml.jpg)
ATSAM3U2EA-CU
Manufacturer Part Number
ATSAM3U2EA-CU
Description
IC MCU 32BIT 128KB FLSH 144LFBGA
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2EA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b, 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
4xUSART, 2xTWI, 5xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
96
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
9.1.3.4
9.1.3.5
32
SAM3U Series
Lock Regions
Security Bit Feature
The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32-
bit internal bus. Its 128-bit wide memory interface increases performance.
The user can choose between high performance or lower current consumption by selecting
either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking
sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system
about the Flash organization, thus making the software generic.
The SAM3U4 (256 KBytes internal Flash version) embeds two EEFC (EEFC0 for Flash0 and
EEFC1 for Flash1) whereas the SAM3U2/1 embeds one EEFC.
In the SAM3U4 (256 KBytes internal Flash version) two Enhanced Embedded Flash Controllers
each manage 16 lock bits to protect 32 regions of the flash against inadvertent flash erasing or
programming commands.
The SAM3U4 (256 KBytes internal Flash version) contains 32 lock regions and each lock region
contains 32 pages of 256 bytes. Each lock region has a size of 8 Kbytes.
The SAM3U2 (128 KBytes internal Flash version) Enhanced Embedded Flash Controller man-
ages 16 lock bits to protect 32 regions of the flash against inadvertent flash erasing or
programming commands.
The SAM3U2 (128 KBytes internal Flash version) contains 16 lock regions and each lock region
contains 32 pages of 256 bytes. Each lock region has a size of 8 Kbytes.
The SAM3U1(64 KBytes internal Flash version) Embedded Flash Controller manages 8 lock bits
to protect 8 regions of the flash against inadvertent flash erasing or programming commands.
The SAM3U1(64 KBytes internal Flash version) contains 8 lock regions and each lock region
contains 32 pages of 256 bytes. Each lock region has a size of 8 Kbytes.
If a locked-region’s erase or program command occurs, the command is aborted and the EEFC
triggers an interrupt.
The lock bits are software programmable through the EEFC User Interface. The command “Set
Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
The SAM3U features a security bit, based on a specific General Purpose NVM bit (GPNVM bit
0). When the security is enabled, any access to the Flash, SRAM, Core Registers and Internal
Peripherals either through the ICE interface or through the Fast Flash Programming Interface, is
forbidden. This ensures the confidentiality of the code programmed in the Flash.
This security bit can only be enabled, through the command “Set General Purpose NVM Bit 0” of
the EEFC User Interface. Disabling the security bit can only be achieved by asserting the
ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated,
all accesses to the Flash, SRAM, Core Registers and Internal Peripherals either through the ICE
interface or through the Fast Flash Programming Interface are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal
6430DS–ATARM–28-Mar-11