ATSAM3U2EA-CU Atmel, ATSAM3U2EA-CU Datasheet - Page 40
![IC MCU 32BIT 128KB FLSH 144LFBGA](/photos/12/13/121356/144-lfbga_sml.jpg)
ATSAM3U2EA-CU
Manufacturer Part Number
ATSAM3U2EA-CU
Description
IC MCU 32BIT 128KB FLSH 144LFBGA
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2EA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b, 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
4xUSART, 2xTWI, 5xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
96
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
10.7
10.8
10.9
10.10 Real-time Clock
10.11 General-Purpose Back-up Registers
10.12 Nested Vectored Interrupt Controller
40
Watchdog Timer
SysTick Timer
Real-time Timer
SAM3U Series
• 16-bit key-protected once-only Programmable Counter
• Windowed, prevents the processor to be in a dead-lock on the watchdog access
• 24-bit down counter
• Self-reload capability
• Flexible system timer
• Real-time Timer, allowing backup of time with different accuracies
• Low power consumption
• Full asynchronous design
• Two hundred year calendar
• Programmable Periodic Interrupt
• Alarm and update parallel load
• Control of alarm and update Time/Calendar Data In
• Eight 32-bit general-purpose backup registers
• Thirty maskable interrupts
• Sixteen priority levels
• Dynamic reprioritization of interrupts
• Priority grouping
• Support for tail-chaining and late arrival of interrupts.
• Processor state automatically saved on interrupt entry, and restored on
– 32-bit Free-running back-up Counter
– Integrates a 16-bit programmable prescaler running on slow clock
– Alarm Register capable to generate a wake-up of the system
– selection of preempting interrupt levels and non preempting interrupt levels.
– back-to-back interrupt processing without the overhead of state saving and
– interrupt exit, with no instruction overhead.
restoration between interrupts.
6430DS–ATARM–28-Mar-11