ATMEGA128L-8MU Atmel, ATMEGA128L-8MU Datasheet - Page 375

• Manufacturer Part Number: ATMEGA128L-8MU
• Description: IC AVR MCU 128K 8MHZ 3V 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128L-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4KB
• Ram Memory Size: 4KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev. 2467M-11/04
Rev. 2467L-05/04
Rev. 2467K-03/04
Rev. 2467J-12/03
Rev. 2467I-09/03
2467V–AVR–02/11
7. Updated
8. Updated Features in
9. Added note in
10. Updated
1. Removed “analog ground”, replaced by “ground”.
2. Updated
3. Added note to
4. Updated
1. Removed “Preliminary” and “TBD” from the datasheet, replaced occurrences of ICx
2. Updated
3. Updated
4. Updated
5. Updated
6. Updated
7. Updated
8. Updated
1. Updated
1. Updated
1. Updated note in
2. Updated
3. Updated values for V
4. Updated
5. Updated description for the JTD bit on
6. Added a note regarding JTAGEN fuse to
Table 132 on page
with ICPx.
page
Table 134 on page
242,
“Serial Peripheral Interface – SPI” on page
“Errata” on page
“Ordering Information” on page
“External Memory Interface” on page
“Device Identification Register” on page
“Electrical Characteristics” on page
“ADC Characteristics” on page
“Typical Characteristics” on page
“Ordering Information” on page
“Errata” on page
“Calibrated Internal RC Oscillator” on page
“JTAG Interface and On-chip Debug System” on page
“Test Access Port – TAP” on page 246
Table 8 on page
Table 11 on page
Table 126 on page
“Input Channel and Gain Selections” on page
“Port C (PC7..PC0)” on page
“XTAL Divide Control Register – XDIV” on page
321. Updated
323.
“Analog to Digital Converter” on page 230
BOT
(BODLEVEL = 1) in
38,
371.
371.
40,
299,
Table 19 on page
Table 114 on page
Figure 114 on page
Table 128 on page
page
325.
Table 118 on page
368.
368.
333.
5.
Table 19 on page
255.
318.
25.
50,
regarding JTAGEN.
253.
285,
Table 22 on page
162.
238.
41.
303,
Table 128 on page
Table 132 on page
288.
243.
50.
48.
ATmega128
36.
56,
Table 96 on
303, and
321, and
375