DSPIC30F6014-20E/PF Microchip Technology, DSPIC30F6014-20E/PF Datasheet - Page 11

• Manufacturer Part Number: DSPIC30F6014-20E/PF
• Description: IC DSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6014-20E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1DM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F601420EPF

12. Module: Timers
13. Module: Output Compare
© 2010 Microchip Technology Inc.
Pairs of 16-bit timers may be combined to form
32-bit timers. For example, Timer2 and Timer3 are
combined into a single 32-bit timer. For this
release of silicon, when a 32-bit timer is prescaled
by ratios other than 1:1, unexpected results may
occur.
Work around
None. The application may only use the 1:1
prescaler for 32-bit timers.
Affected Silicon Revisions
A glitch will be produced on an output compare pin
under the following conditions:
• The user software initially drives the I/O pin
• The Output Compare module is configured and
When these events occur, the Output Compare
module will drive the pin low for one instruction
cycle (T
Work around
None. However, the user may use a timer interrupt
and write to the associated PORT register to
control the pin manually.
Affected Silicon Revisions
A3
A3
X
high using the Output Compare module or a
write to the associated PORT register.
enabled to drive the pin low at some point in later
time (OCxCON = 0x0002 or OCxCON = 0x0003).
X
CY
B1
B1
X
X
) after the module is enabled.
B2
B2
X
X
dsPIC30F6011/6012/6013/6014
14. Module: ADC
Input channel scanning allows the ADC to acquire
and convert signals on a selected set of “MUX A”
input pins in sequence. This function is controlled
by the CSCNA bit (ADCON2<10>) and the
ADCSSL SFR.
The ALTS bit (ADCON2<0>), when set, allows the
ADC to alternately acquire and convert a “MUX A”
input signal and a “MUX B” input signal in an
interleaved fashion.
When both CSCNA and ALTS are set, the ADC
module should scan MUX A input pins while
alternating with a fixed MUX B input pin. However,
for this release of silicon, when both features are
enabled simultaneously, the last input pin enabled
for channel scanning in the ADCSSL SFR is not
scanned. Thus, the ADC converts one channel
less than the number specified in the scan
sequence. Note that this erratum does not affect
devices that have a 10-bit 500 ksps ADC.
Work around
The user may enable an extra (“dummy”) input pin
in the channel-scanning sequence. For example, if
it is desirable to scan pins AN3, AN4 and AN5 on
the set of MUX A inputs while interleaving
conversion from AN6 on the MUX B input, the user
may configure the ADC as follows:
For the configuration above, AN15 is the dummy
input that will not be scanned. On the A/D interrupt,
the A/D buffer will contain conversions from the
following pins in sequence:
Affected Silicon Revisions
A3
- ADCON2 = 0x041D
- ADCHS = 0x0600
- ADCSSL = 0x8038
- ADCBUF0 = AN3
- ADCBUF1 = AN6
- ADCBUF2 = AN4
- ADCBUF3 = AN6
- ADCBUF4 = AN5
- ADCBUF5 = AN6
- ADCBUF6 = AN3
- ADCBUF7 = AN6
X
B1
X
B2
X
DS80456D-page 11