ATMEGA2561V-8AU Atmel, ATMEGA2561V-8AU Datasheet - Page 85
ATMEGA2561V-8AU
Manufacturer Part Number
ATMEGA2561V-8AU
Description
IC AVR MCU 256K 8MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA2561V-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
6
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA2561V-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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2549M–AVR–09/10
Table 12-13. Overriding Signals for Alternate Functions PD7:PD4
Table 12-14. Overriding Signals for Alternate Functions in PD3:PD0
Note:
Signal Name
Signal Name
DIEOE
DIEOV
DDOE
PUOE
PUOV
DDOV
PVOE
PVOV
DIEOE
DIEOV
DDOE
PUOE
PUOV
DDOV
PVOE
PVOV
AIO
AIO
DI
DI
1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure and the digital logic of the TWI module.
PD3/INT3/TXD1
INT3 ENABLE
INT3 INPUT
T0 INPUT
PD7/T0
TXEN1
TXEN1
TXEN1
TXD1
0
0
0
0
0
0
0
0
–
0
1
1
–
ATmega640/1280/1281/2560/2561
T1 INPUT
PD6/T1
INT2 INPUT/RXD1
PD2/INT2/RXD1
PORTD2 • PUD
INT2 ENABLE
0
0
0
0
0
0
0
0
–
RXEN1
RXEN1
0
0
0
1
–
XCK1 OUTPUT ENABLE
XCK1 OUTPUT ENABLE
XCK1 OUTPUT
XCK1 INPUT
PD5/XCK1
PORTD1 • PUD
PD1/INT1/SDA
INT1 ENABLE
INT1 INPUT
SDA INPUT
SDA_OUT
0
0
1
0
0
–
TWEN
TWEN
TWEN
0
1
(1)
PORTD0 • PUD
PD0/INT0/SCL
INT0 ENABLE
INT0 INPUT
SCL INPUT
SCL_OUT
ICP1 INPUT
TWEN
TWEN
TWEN
PD4/ICP1
0
1
0
0
0
0
0
0
0
0
–
85
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