ST7FLITEU09M3 STMicroelectronics, ST7FLITEU09M3 Datasheet - Page 49
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ST7FLITEU09M3
Manufacturer Part Number
ST7FLITEU09M3
Description
IC MCU 8BIT 2K FLASH 8SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITEU05M6.pdf
(139 pages)
Specifications of ST7FLITEU09M3
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
ST7FLITEUx
Core
ST7
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
ICC
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
5
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
ST7LITEU05 ST7LITEU09
8.4.4
Note:
Table 13.
Register description
System integrity (SI) control/status register (SICSR)
Reset value: 0000 0x00 (0xh)
Bit 7 = Reserved, must be kept cleared.
Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits
Bits 4:3 = Reserved, must be kept cleared.
Bit 2 = LVDRF LVD reset flag
If the selected clock source is one of the two internal ones, and if V
selected LVD threshold during less than T
even if the device is reset by the LVD. If the selected clock source is the external clock
(CLKIN), the flag is never set if the reset occurs during Halt mode. In run mode the flag is set
only if f
Bit 1 = AVDF Voltage Detector flag
Bit 0 = AVDIE Voltage Detector interrupt enable
AVD event
These bits, as well as CR[9:2] bits in the RCCR register must be written immediately
after reset to adjust the RC oscillator frequency and to obtain the required accuracy.
Refer to
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared when read. See WDGRF flag description in
Section 11.1 on page 68
LVDRF bit value is undefined.
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt
request is generated when the AVDF bit is set. Refer to
0: V
1: V
This bit is set and cleared by software. It enables an interrupt to be generated when the
AVDF flag is set. The pending interrupt information is automatically cleared when
software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
0
7
CLKIN
DD
DD
Interrupt event
over AVD threshold
under AVD threshold
Description of interrupt events
is greater than 10 MHz.
Section 7.2 on page
CR1
CR0
for more details. When the LVD is disabled by option byte, the
32.
Event
0
AVDF
fl
Read/write
AWU_RC
ag
(33 µs typ.), the LVDRF flag cannot be set
0
control
Enable
AVDIE
bit
LVDRF
Figure 21
DD
from
Wait
Exit
Yes
remains below the
for additional details;
AVDF
Interrupts
from
Exit
Halt
AVDIE
No
0
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