ST7FLITE20F2M6 STMicroelectronics, ST7FLITE20F2M6 Datasheet - Page 52
ST7FLITE20F2M6
Manufacturer Part Number
ST7FLITE20F2M6
Description
IC MCU 8BIT 8K FLASH 20SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITE20F2B6.pdf
(133 pages)
Specifications of ST7FLITE20F2M6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7FLITE2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
4 bit
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLIT2-COS/COM, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
13 bit
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5517 - EVAL BOARD 1PHASE ENERGY METER497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Other names
497-4857
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
ST7LITE2
11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
11.1.2 Main Features
■
■
■
Figure 33. Watchdog Block Diagram
52/133
1
Programmable free-running downcounter (64
increments of 16000 CPU cycles)
Programmable reset
Reset (if watchdog activated) when the T6 bit
reaches zero
f
CPU
WDGA
RESET
T6
T5
WATCHDOG CONTROL REGISTER (CR)
7-BIT DOWNCOUNTER
CLOCK DIVIDER
T4
÷16000
T3
■
■
11.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 16000 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
30µs.
T2
Optional
(configurable by option byte)
Hardware Watchdog selectable by option byte
T1
reset
T0
on
HALT
instruction