Z8F0822PJ020SG Zilog, Z8F0822PJ020SG Datasheet - Page 133
![IC ENCORE MCU FLASH 8K 28DIP](/photos/6/57/65755/269-28-dip_sml.jpg)
Z8F0822PJ020SG
Manufacturer Part Number
Z8F0822PJ020SG
Description
IC ENCORE MCU FLASH 8K 28DIP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F0822PJ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Controller Family/series
Z8
No. Of I/o's
19
Ram Memory Size
1KB
Cpu Speed
20MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
Z8F082xx
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
19
Number Of Timers
2
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4208
Z8F0822PJ020SG
Z8F0822PJ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F0822PJ020SG
Manufacturer:
Zilog
Quantity:
45
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PS022517-0508
SPI Baud Rate Generator
necessary for SS to deassert between characters to generate the interrupt. The SPI in
SLAVE mode also generates an interrupt if the SS signal deasserts prior to transfer of all
the bits in a character (see description of Slave Abort Error). Writing a 1 to the IRQ bit in
the SPI Status Register clears the pending SPI interrupt request. The
cleared to 0 by the ISR to generate future interrupts. To start the transfer process, an SPI
interrupt can be forced by software writing a 1 to the STR bit in the SPICTL Register.
If the SPI is disabled, an SPI interrupt can be generated by a BRG time-out. This timer
function must be enabled by setting the BIRQ bit in the SPICTL Register. This BRG
time-out does not set the IRQ bit in the SPISTAT Register, just the SPI interrupt bit in the
interrupt controller.
In SPI MASTER mode, the BRG creates a lower frequency serial clock (SCK) for data
transmission synchronization between the Master and the external Slave. The input to the
BRG is the system clock. The SPI Baud Rate High and Low Byte Registers combine to
form a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator. The SPI baud
rate is calculated using the following equation:
Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value
of (2 X 65536 = 131072).
When the SPI is disabled, BRG functions as a basic 16-bit timer with interrupt on
time-out. Follow the steps below to configure BRG as a timer with interrupt on time-out:
1. Disable the SPI by clearing the SPIEN bit in the SPI Control Register to 0.
2. Load the desired 16-bit count value into the SPI Baud Rate High and Low Byte
3. Enable BRG timer function and associated interrupt by setting the BIRQ bit in the SPI
When configured as a general-purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0] ]
registers.
Control Register to 1.
SPI Baud Rate (bits/s)
=
System Clock Frequency (Hz)
------------------------------------------------------------------------------ -
2xBRG[15:0]
Z8 Encore! XP
Product Specification
Serial Peripheral Interface
IRQ
®
bit must be
F0822 Series
120
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