ST7FLITE39F2M3 STMicroelectronics, ST7FLITE39F2M3 Datasheet - Page 117
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ST7FLITE39F2M3
Manufacturer Part Number
ST7FLITE39F2M3
Description
IC MCU 8BIT 8K FLASH 20SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST7FLITE39F2M3
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7FLITE3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
LINSCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
For Use With
497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-6398 - BOARD EVAL ST7FLITE39/STM1403497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5514 - EVAL BOARD THERMO CONTROL REFRIG497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLITE39F2M3TR
Manufacturer:
ST
Quantity:
20 000
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
SCICR2 register is set, the LHDM bit selects the
Wake-Up method (replacing the WAKE bit).
0: LIN Synch Break Detection Method
1: LIN Identifier Field Detection Method
Bit 2 = LHIE LIN Header Interrupt Enable
This bit is set and cleared by software. It is only us-
able in LIN Slave mode.
0: LIN Header Interrupt is inhibited.
1: An SCI interrupt is generated whenever
Bit 1 = LHDF LIN Header Detection Flag
This bit is set by hardware when a LIN Header is
detected and cleared by a software sequence (an
access to the SCISR register followed by a read of
the SCICR3 register). It is only usable in LIN Slave
mode.
0: No LIN Header detected.
1: LIN Header detected.
Notes: The header detection method depends on
the LHDM bit:
Bit 0 = LSF LIN Synch Field State
This bit indicates that the LIN Synch Field is being
analyzed. It is only used in LIN Slave mode. In
Auto Synchronization Mode (LASE bit = 1), when
the SCI is in the LIN Synch Field State it waits or
counts the falling edges on the RDI line.
It is set by hardware as soon as a LIN Synch Break
is detected and cleared by hardware when the LIN
Synch Field analysis is finished (see
This bit can also be cleared by software to exit LIN
Synch State and return to idle mode.
0: The current character is not the LIN Synch Field
1: LIN Synch Field State (LIN Synch Field under-
LHDF = 1.
going analysis)
– If LHDM = 0, a header is detected as a LIN
– If LHDM = 1, a header is detected as a LIN
Synch Break.
Identifier, meaning that a LIN Synch Break
Field + a LIN Synch Field + a LIN Identifier
Field have been consecutively received.
Figure
65).
Figure 65. LSF Bit Set and Clear
LIN DIVIDER REGISTERS
LDIV is coded using the two registers LPR and LP-
FR. In LIN Slave mode, the LPR register is acces-
sible at the address of the SCIBRR register and
the LPFR register is accessible at the address of
the SCIETPR register.
LIN PRESCALER REGISTER (LPR)
Read/Write
Reset Value: 0000 0000 (00h)
LPR[7:0] LIN Prescaler (mantissa of LDIV)
These 8 bits define the value of the mantissa of the
LIN Divider (LDIV):
Caution: LPR and LPFR registers have different
meanings when reading or writing to them. Conse-
quently bit manipulation instructions (BRES or
BSET) should never be used to modify the
LPR[7:0] bits, or the LPFR[3:0] bits.
LPR7
LSF bit
11 dominant bits
7
LPR[7:0]
LIN Synch
FEh
FFh
00h
01h
Break
...
LPR6
LPR5
LIN Synch
Field
LPR4
Rounded Mantissa (LDIV)
SCI clock disabled
parity bits
LPR3
254
255
Identifier
Field
...
1
LPR2
ST7LITE3xF2
LPR1
117/173
LPR0
0