ST72C254G2M6 STMicroelectronics, ST72C254G2M6 Datasheet - Page 36
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ST72C254G2M6
Manufacturer Part Number
ST72C254G2M6
Description
IC MCU 8BIT 8K FLASH SOIC-28
Manufacturer
STMicroelectronics
Series
ST7r
Datasheets
1.INDART-ST72C254.pdf
(3 pages)
2.ST72C104G1M6.pdf
(141 pages)
3.ST72C215G2M6.pdf
(140 pages)
Specifications of ST72C254G2M6
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3.2 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
ST7
No. Of I/o's
22
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
ST72C2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
3.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDT1-DVP2/US
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72C254G2M6
Manufacturer:
ST
Quantity:
20 000
ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
10 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external in-
terrupts or the I/O alternate functions.
10.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the ISxx bits of the Miscellaneous register and the
OPTION BYTE. This control allows having two ful-
ly independent external interrupt source sensitivi-
ties with configurable sources (using EXTIT option
bit) as shown in
Each external interrupt source can be generated
on four different events on the pin:
■
■
■
■
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I bit of the CC register is set to 1 (inter-
rupt masked). See I/O port register and Miscella-
neous register descriptions for more details on the
programming.
10.2 I/O PORT ALTERNATE FUNCTIONS
The MISCR registers manage four I/O port miscel-
laneous alternate functions:
■
■
These functions are described in detail in the
tion 10.3 "MISCELLANEOUS REGISTER DE-
SCRIPTION" on page
36/141
– SS pin internal control to use the PB7 I/O port
– Master output capability on MOSI pin (PB4)
– Slave output capability on MISO pin (PB5) de-
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Main clock signal (f
SPI pin configuration:
function while the SPI is active.
deactivated while the SPI is active.
activated while the SPI is active.
Figure 23
CPU
37.
) output on PC2
and
Figure
24.
Sec-
Figure 23. Ext. Interrupt Sensitivity (EXTIT=0)
Figure 24. Ext. Interrupt Sensitivity (EXTIT=1)
PC5
PC0
PA7
PA0
PB7
PB0
PC5
PC0
PA7
PA0
PB7
PB0
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
SOURCE
SOURCE
SOURCE
SOURCE
ei0
ei1
ei0
ei1
SENSITIVITY
SENSITIVITY
IS00
IS10
SENSITIVITY
SENSITIVITY
IS00
IS10
CONTROL
CONTROL
CONTROL
CONTROL
MISCR1
MISCR1
MISCR1
MISCR1
IS01
IS11
IS01
IS11