ST72C254G2M6 STMicroelectronics, ST72C254G2M6 Datasheet - Page 49
![IC MCU 8BIT 8K FLASH SOIC-28](/photos/6/56/65690/stmicroelectronics-28-soic_sml.jpg)
ST72C254G2M6
Manufacturer Part Number
ST72C254G2M6
Description
IC MCU 8BIT 8K FLASH SOIC-28
Manufacturer
STMicroelectronics
Series
ST7r
Datasheets
1.INDART-ST72C254.pdf
(3 pages)
2.ST72C104G1M6.pdf
(141 pages)
3.ST72C215G2M6.pdf
(140 pages)
Specifications of ST72C254G2M6
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3.2 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
ST7
No. Of I/o's
22
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
ST72C2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
3.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDT1-DVP2/US
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72C254G2M6
Manufacturer:
ST
Quantity:
20 000
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OC i HR reg-
2. If the OC i E bit is not set, the OCMP i pin is a
3. When the timer clock is f
4. The output compare functions can be used both
5. The value in the 16-bit OC
Figure 32. Output Compare Block Diagram
16-bit
ister, the output compare function is inhibited
until the OC i LR register is also written.
general I/O port and the OLVL i bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
OCMP i are set while the counter value equals
the OC i R register value (see
53). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
external clock mode, OCF i and OCMP i are set
while the counter value equals the OC i R regis-
ter value plus 1 (see
for generating external events on the OCMP i
pins even if the input capture mode is also
used.
OLV i bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
16 BIT FREE RUNNING
OC1R Register
OUTPUT COMPARE
16-bit
CIRCUIT
OC2R Register
COUNTER
16-bit
Figure 34 on page
CPU
i
R register and the
CPU
Figure 33 on page
/4, f
/2, OCF i and
OC1E
CPU
OCIE
OC2E
OCF1
/8 or in
53).
FOLV2 FOLV1
ST72104G, ST72215G, ST72216G, ST72254G
Forced Compare Output capability
When the FOLV i bit is set by software, the OLVL i
bit is copied to the OCMP i pin. The OLV i bit has to
be toggled in order to toggle the OCMP i pin when
it is enabled (OC i E bit=1). The OCF i bit is then not
set by hardware, and thus no interrupt request is
generated.
FOLVL i bits have no effect in either One-Pulse
mode or PWM mode.
(Control Register 2) CR2
(Control Register 1) CR1
OCF2
CC1
(Status Register) SR
OLVL2
CC0
0
0
OLVL1
0
Latch
Latch
1
2
OCMP2
OCMP1
Pin
Pin
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