Z16F3211FI20AG Zilog, Z16F3211FI20AG Datasheet - Page 170
Z16F3211FI20AG
Manufacturer Part Number
Z16F3211FI20AG
Description
IC ZNEO MCU FLASH 32K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Specifications of Z16F3211FI20AG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-BQFP
Data Bus Width
16 bit
Data Ram Size
2 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Table 82. LIN-UART Status 0 Register – Standard UART Mode (UxSTAT0)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
LIN-UART Status 0 Register
RDA
R
7
0
The LIN-UART Status 0 register identifies the current LIN-UART operating configuration
and status.
Table 83
RDA—Receive Data Available
This bit indicates that the LIN-UART receive data register has received data. Reading the
LIN-UART receive data register clears this bit.
0 = The LIN-UART receive data register is empty.
1 = There is a byte in the LIN-UART receive data register.
PE—Parity Error
This bit indicates that a parity error has occurred. Reading the receive data register clears
this bit.
0 = No parity error occurred.
1 = A parity error occurred.
OE—Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the receive data register has not been read. Reading the receive data register
clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
FE—Framing Error
This bit indicates that a framing error (no Stop bit following data reception) is detected.
Reading the receive data register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
BRKD—Break Detect
This bit indicates that a break has occurred. If the data bits, parity/multiprocessor bit, and
Stop bit(s) are all zeros then this bit is set to 1. Reading the receive data register clears this
bit.
on page 155 describes the Status 0 register for LIN mode.
PE
Table 82
R
6
0
below describes the Status 0 register for standard UART mode.
OE
R
5
0
P R E L I M I N A R Y
FF-E201H, FF-E211H
FE
R
4
0
BRKD
R
3
0
TDRE
R
2
1
Product Specification
ZNEO
TXE
1
R
1
Z16F Series
LIN-UART
CTS
X
R
0
154
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