Z16F3211FI20AG Zilog, Z16F3211FI20AG Datasheet - Page 338
Z16F3211FI20AG
Manufacturer Part Number
Z16F3211FI20AG
Description
IC ZNEO MCU FLASH 32K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Specifications of Z16F3211FI20AG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-BQFP
Data Bus Width
16 bit
Data Ram Size
2 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Manufacturer
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Table 174. OCD Status Register (OCDSTAT)
PS022008-0810
BITS
FIELD
RESET
R/W
OCD Status Register
DBGHALT DBGBRK
BRKHALT bit is set.
0 = The device is running.
1 = The device is in Debug Halt mode.
BRKHALT—Breakpoint halt
This bit determines what action the OCD takes when a Breakpoint occurs. If this bit is set
to one, then the DBGHALT bit is automatically set to one when a breakpoint occurs. If
BRKHALT is zero, then the CPU will loop on the breakpoint.
0 = CPU loops on current instruction when breakpoint occurs.
1 = A Breakpoint sets DBGHALT to one.
BRKEN—Enable breakpoints
This bit controls the behavior of the
default, these generate an illegal instruction system trap. If this bit is set to one, these
events generate a Breakpoint instead of a system trap. The resulting action depends upon
the BRKHALT bit.
0 =
1 =
DBGSTOP—Debug Stop mode
This bit controls the system clock behavior in STOP mode. When set to one, the system
clock will continue to operate in STOP mode.
0 = Stop mode debug disabled. system clock stops in STOP mode.
1 = Stop mode debug enabled. system clock runs in STOP mode.
Reserved
This bit is reserved and must be written to zero.
STEP—Single step an instruction
This bit is used to single step an instruction when in Debug Halt Mode. This bit is auto-
matically cleared after an instruction is executed.
0 = Idle
1 = Single Step an Instruction.
The
the system.
R
7
0
BRK
BRK
OCD Status Register (OCDSTAT)
instruction and hardware breakpoint generates system trap.
instruction and hardware breakpoint generates a breakpoint.
R
6
0
HALT
R
5
0
P R E L I M I N A R Y
STOP
BRK
R
4
0
reports status information about the current state of
instruction and the hardware breakpoint. By
RPEN
3
R
0
Reserved
R
2
0
Product Specification
ZNEO
TDRF
On-Chip Debugger
R
1
0
Z16F Series
RDRE
R
0
1
322
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