Z16F3211FI20AG Zilog, Z16F3211FI20AG Datasheet - Page 194
Z16F3211FI20AG
Manufacturer Part Number
Z16F3211FI20AG
Description
IC ZNEO MCU FLASH 32K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Specifications of Z16F3211FI20AG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-BQFP
Data Bus Width
16 bit
Data Ram Size
2 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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ESPI Register Overview
PS022008-0810
Comparison with Basic SPI Block
controlled by the SSIO bit of the ESPI mode register. The SS signal is an input on slave
devices and is an output on the active master device. Slave devices ignore transactions on
the bus unless their slave select input is asserted. In SPI MASTER mode, additional GPIO
pins are required to provide Slave Selects if there is more than one slave device.
The ESPI Control/Status Registers are summarized in
accessed by either Word (16-bit) or Byte operations.
Table 93. ESPI Registers
The ESPI module includes many enhancements when compared to the simpler SPI module
in other Z8 Encore!
and the SPI module as follows:
•
•
•
•
•
•
Word Address
XXXXX0
XXXXX2
XXXXX4
XXXXX6
Transmit and receive data buffer register added to support higher performance.
Multiple interrupt sources (transmit data, receive data, errors). SPI module only has
data transfer complete interrupt.
DMA controller interface (separate transmit and receive interfaces).
Register addresses redefined to facilitate 16-bit transfers on the ZNEO
Transmit data command register – new register to facilitate DMA interface and
Control register:
– IRQE changed to DIRQE. This allows data interrupts to be disabled when using
– STR bit on the SPI module replaced with ESPIEN1. SPIEN replaced with
– BIRQ replaced with BRGCTL.
improve performance with 16-bit transfers. SSV and TEOF is set on same cycle on
which the data register is written.
DMA but still allow error interrupts.
ESPIEN0. This enhancement allows unidirectional transfers which minimizes
software or DMA overhead.
®
parts. This section highlights the differences between the ESPI module
Even Address
Data
Control
Status
Baud Rate High
P R E L I M I N A R Y
Odd Address
Transmit Data Command
Mode
State
Baud Rate Low
Enhanced Serial Peripheral Interface
Table
93. These registers are
Product Specification
ZNEO
®
Z16F Series.
Z16F Series
178
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