STR710RZH6 STMicroelectronics, STR710RZH6 Datasheet - Page 45

• Manufacturer Part Number: STR710RZH6
• Description: MCU ARM7 32BIT 64-LFBGA
• Manufacturer: STMicroelectronics
• Series: STR7r

Specifications of STR710RZH6

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, HDLC, I²C, SmartCard, SPI, UART/USART, USB
• Peripherals: PWM, WDT
• Number Of I /o: 48
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LFBGA
• Processor Series: STR710x
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: CAN, EMI, USB
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MCBSTR7, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: STX-PRO/RAIS, STX-RLINK, STR79-RVDK/CPP, STR79-RVDK, STR79-RVDK/UPG
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• For Use With: MCBSTR7UME - MCBSTR7 + ULINK-ME DEV KITMCBSTR7 - BOARD EVAL STM STR71X SERIES497-4516 - BOARD EVAL FOR STR71X SER MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

STR71xF
Table 22.
Table 23.
1. Clock selected is CK2_16, Main VReg OFF and Flash in power-down
2. The CLK clock is derived from the external oscillator.
3. Refer to Figure 7. Reset General Timing in the STR71xF Reference Manual (UM0084)
∆t
t
f
t
Symbol
Symbol
t
WULPWFI
PLLCLK2
WUSTOP
WUSTBY
t
LOCK2
JITTER2
f
PLL2
PLL multiplier output
clock
PLL input clock
PLL lock time
PLL jitter (peak to peak)
Wakeup from LPWFI mode
Wakeup from STOP mode
Wakeup from STANDBY mode
PLL2 characteristics
Low-power mode wakeup timing
Parameter
Parameter
FREF_RANGE = 0
FREF_RANGE = 1
FREF_RANGE = 0
Stable Input Clock
Stable V
FREF_RANGE = 1
Stable Input Clock
Stable V
t
Global Output division = 32
(Output Clock = 2 MHz)
PLL
= 4 MHz, MX[1:0]=’11’
Test conditions
33IOPLL
33IOPLL
, V
, V
18
18
+ 8 CLK2 Cycles
Min
2048 CLK Cycles
1.5
3.0
Electrical parameters
Value
2048
26
Typ
Typ
0.7
(1)
Max
140
300
600
3.0
2
5
(3)
Cycles
Cycles
MHz
MHz
MHz
Unit
Unit
CLK
µs
µs
ns
µs
(2)
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