W77E058A40DL Nuvoton Technology Corporation of America, W77E058A40DL Datasheet - Page 27

• Manufacturer Part Number: W77E058A40DL
• Description: IC MCU 8-BIT 32K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W77r

Specifications of W77E058A40DL

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, Serial Port
• Peripherals: POR, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP
• Cpu Family: W77
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: UART
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

RS.1-0: Register bank select bits:
OV:
F1:
P:
Watchdog Control
SMOD_1:This bit doubles the Serial Port 1 baud rate in mode 1, 2, and 3 when set to 1.
POR:
WDIF: Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will set this bit
WTRF: Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a
EWT:
RWT: Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know state. It also
The WDCON SFR is set to a 0x0x0xx0b on an external reset. WTRF is set to a 1 on a Watchdog timer
reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set to 1
by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets.
All the bits in this SFR have unrestricted read access. POR, EWT, WDIF and RWT require Timed
Access procedure to write. The remaining bits have unrestricted write accesses.
Accumulator
ACC.7-0:The A (or ACC) register is the standard 8052 accumulator.
Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as
a result of the previous operation, or vice-versa.
User Flag 1: General purpose flag that can be set or cleared by the user by software.
Power-on reset flag. Hardware will set this flag on a power up condition. This flag can be read
or written by software. A write by software is the only way to clear this bit once it is set.
to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this bit
indicates that the time-out period has elapsed. This bit must be cleared by software.
reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit.
This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer
will have no affect on this bit.
helps in resetting the watchdog timer before a time-out occurs. Failing to set the RWT before
time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a watchdog
timer reset will be generated if EWT is set. This bit is self-clearing by hardware.
Parity flag: Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.
Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function.
RS1
Mnemonic: WDCON
Mnemonic: ACC
0
0
1
1
Bit:
Bit:
RS0
0
1
0
1
SMOD_1
ACC.7
7
7
Register bank
ACC.6
POR
6
6
0
1
2
3
ACC.5
- 27 -
5
5
-
ACC.4
Address
00-07h
08-0Fh
10-17h
18-1Fh
4
4
-
Publication Release Date: April 17, 2007
ACC.3
WDIF
3
3
Address: D8h
Address: E0h
WTRF
ACC.2
2
2
W77E058A
ACC.1
EWT
1
1
Revision A10
ACC.0
RWT
0
0