ST92F124R9TB STMicroelectronics, ST92F124R9TB Datasheet - Page 427
ST92F124R9TB
Manufacturer Part Number
ST92F124R9TB
Description
IC MCU 8BIT 64K MEMORY 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F124R9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F12x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
6 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F124R9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
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KNOWN LIMITATIONS (Cont’d)
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit fre-
q u e n c y o f 1 9 2 0 0 b a u d ( f C P U = 8 M H z a n d
SCIBRR=0xC9), the wrong break duration occur-
rence is around 1%.
Analysis
The LIN protocol specifies a minimum of 13 bits for
the break duration, but there is no maximum value.
Nevertheless, the maximum length of the header
is specified as (14+10+10+1)x1.4=49 bits. This is
composed of:
- the synch break field (14 bits),
- the synch field (10 bits),
- the identifier field (10 bits).
Every LIN frame starts with a break character.
Adding an idle character increases the length of
each header by 10 bits. When the problem oc-
curs, the header length is increased by 11 bits and
becomes ((14+11)+10+10+1)=45 bits.
To conclude, the problem is not always critical for
LIN communication if the software keeps the time
ST92F124/F150/F250 - KNOWN LIMITATIONS
between the sync field and the ID smaller than 4
bits, i.e. 208us at 19200 baud.
The workaround is the same as for SCI mode but
considering the low probability of occurrence (1%),
it may be better to keep the break generation se-
quence as it is.
13.8.10 LIN MASTER MODE NOT AVAILABLE
ON SCI-A
LIN Synch Breaks (13 low bits) generation is not
possible on SCI-A. LINE bit has no effect on break
length.
13.8.11 LIMITATIONS ON LQFP64 DEVICES
13.8.11.1
LQFP64 DEVICES
ADC Channels from AIN0 to AIN7 are not present
on LQFP64 devices.
13.8.11.2 EFT0 AND EFT1 NOT AVAILABLE ON
LQFP64 DEVICES
Extended Function Timers are not present on
LQFP64 devices.
AIN[7:0]
NOT
AVAILABLE
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