ST92F124V1QB STMicroelectronics, ST92F124V1QB Datasheet - Page 422
ST92F124V1QB
Manufacturer Part Number
ST92F124V1QB
Description
IC MCU 8BIT 128K MEMORY 100-PQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F124V1QB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
77
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-QFP
Processor Series
ST92F12x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
4 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F124V1QB
Manufacturer:
MAXIM
Quantity:
56
Company:
Part Number:
ST92F124V1QB
Manufacturer:
STMicroelectronics
Quantity:
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Part Number:
ST92F124V1QB
Manufacturer:
ST
Quantity:
20 000
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ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
Here is an example of a patch for the MFT1 using
DMA in ouput compare mode, inserted at the be-
ginning of the MFT0 interrupt routine:
spp #8 ;Set to page 8 (mft1)
tm T_IDMR,#0x08 ;test mft0 OCMP dma
mask bit
jxnz MFT0_it_routine
cpw DMA_CNT1,#0 ;If the DMA count is
not at zero the block did not complete
jxeq MFT0_it_routine
and T_FLAGR,#11011111b ;Clear dma
compare interrupt request
422/429
1
or T_IDMR,#0x08 ;Re-enable the com-
pare 0 dma
MFT0_it_routine: ;MFT0 interrupt rou-
tine code
In addition, the peripheral DMA priorities must be
organized so that the MFT DMA priorities are the
highest. This way the impact is limited: DMA re-
quests with the wrong Mask Bit Reset are serv-
iced.
Workaround Limitation
If the counter event period is too short, the failure
recovery in the interrupt routines will not work.
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