STR912FAW46X6T STMicroelectronics, STR912FAW46X6T Datasheet - Page 88

• Manufacturer Part Number: STR912FAW46X6T
• Description: MCU 16/32BIT FLASH 128-TQFP
• Manufacturer: STMicroelectronics
• Series: STR9r

Specifications of STR912FAW46X6T

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: STR912x
• Core: ARM966E-S
• 3rd Party Development Tools: EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical characteristics
7.12.5
88/102
SPI electrical characteristics
V
Table 46.
Figure 30. SPI slave timing diagram with CPHA = 0
MISO
MOSI
DDQ
1/t
t
t
Symbol
w(SCLKH)
w(SCLKL)
t
t
t
t
r(SCLK)
f(SCLK)
t
t
t
t
dis(SO)
t
t
f
t
t
su(SS)
t
su(MI)
t
v(MO)
h(MO)
NSS
SCLK
c(SCLK)
su(SI)
a(SO)
v(SO)
h(SO)
h(SS)
h(MI)
h(SI)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
OUTPUT
INPUT
= 2.7 - 3.6 V, V
INPUT
SPI clock frequency
SPI clock rise and fall times 50pF load
SS setup time
SS hold time
SCLK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
SPI electrical characteristics
t
a(SO)
t
su(NSS)
t
su(SI)
Parameter
DD
= 1.65 - 2 V, T
t
t
MSB IN
w(SCLKH)
w(SCLKL)
MSB OUT
Doc ID 13495 Rev 6
t
t
h(SI)
c(SCLK)
A
t
Master
Slave
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable
edge)
Master (before capture
edge)
v(SO)
= -40 / 85 °C unless otherwise specified.
Test conditions
BIT6 OUT
BIT1 IN
t
h(SO)
t
t
r(SCLK)
f(SCLK)
TBD
TBD
0.25
0.25
Typ
1
1
1
5
6
0
LSB IN
Value
0.1
LSB OUT
t
h(NSS)
Max
24
STR91xFAxxx
6
4
6
6
t
V/ns
dis(SO)
t
MHz
Unit
PCLK