ST10F276-4TR3 STMicroelectronics, ST10F276-4TR3 Datasheet - Page 220

• Manufacturer Part Number: ST10F276-4TR3
• Description: MCU 16BIT 832K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276-4TR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 48MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Electrical characteristics
23.8.22
Table 108. Master mode
1. Maximum baud rate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and <SSCBR> set to
2. Formula for SSC Clock Cycle time:
220/231
t
t
t
t
t
t
t
t
t
t
t
300
301
302
303
304
305
306
307p
308p
307
308
Symbol
‘3h’, or with 48 MHz CPU clock and <SSCBR> set to ‘2h’. When 40 MHz CPU clock is used the maximum
baud rate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>.
Value ‘1h’ for <SSCBR> may be used only with CPU clock equal to (or lower than) 32 MHz (after checking
that timings are in line with the target slave).
t
Where <SSCBR> represents the content of the SSC baud rate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t
300
CC
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
= 4 TCL x (<SSCBR> + 1)
SSC clock cycle time
SSC clock high time
SSC clock low time
SSC clock rise time
SSC clock fall time
Write data valid after shift edge
Write data hold after shift edge
3
Read data setup time before
latch edge, phase error
detection on (SSCPEN = 1)
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
Read data setup time before
latch edge, phase error
detection off (SSCPEN = 0)
Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
High-speed synchronous serial interface (SSC) timing modes
Master mode
V
DD
= 5V ±10%, V
Parameter
300
is 125ns (corresponding to 8Mbaud)
(2)
SS
= 0V, T
A
Max. baud rate 6.6Mbaud
= -40 to +125°C, C
(<SSCBR> = 0002h)
Min.
37.5
150
@ f
63
- 2
50
25
0
-
CPU
= 40 MHz
Max.
150
10
15
-
-
L
= 50pF
(1)
(<SSCBR> = 0001h - FFFFh)
2TCL + 12.5
t
300
8TCL
4TCL
2TCL
Min.
Variable baud rate
/ 2 - 12
- 2
0
-
262144 TCL
Max.
10
15
-
-
ST10F276E
Unit
ns