ST10F276-4T3 STMicroelectronics, ST10F276-4T3 Datasheet

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... Individually programmable as input, output or special function – Programmable threshold (hysteresis) ■ Idle, power down and stand-by modes ■ Single voltage supply: 5V ±10% (embedded regulator for 1.8 V core supply) Rev 2 ST10F276E LQFP144 ( 1.4mm) (Low profile plastic quad flat package) 1/231 www.st.com 1 ...

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... Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 XFlash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Flash non-volatile write protection X register low . . . . . . . . . . . . . . . . . . 37 Flash non-volatile write protection X register high . . . . . . . . . . . . . . . . . 38 Flash non-volatile write protection I register low . . . . . . . . . . . . . . . . . . 38 Flash non-volatile write protection I register high . . . . . . . . . . . . . . . . . 38 Flash non-volatile access protection register ST10F276E ...

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... ST10F276E 4.4.7 4.4.8 4.4.9 4.4.10 4.4.11 4.5 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.6 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.1 Selection among user-code, standard or alternate bootstrap . . . . . . . . . 46 5.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.3 Standard bootstrap with UART (RS232 or K-Line ...

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... I/O’s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4/231 Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ST10 configuration in alternate boot mode . . . . . . . . . . . . . . . . . . . . . . 66 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Exiting alternate boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Alternate boot user software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 User/alternate mode signature integrity check . . . . . . . . . . . . . . . . . . . 67 Alternate boot user software aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 68 EMUCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Internal decoding of test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ST10F276E ...

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... ST10F276E 12.2.1 12.2.2 12.3 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 13 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 14 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 94 14.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 96 15 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 16 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 16.1 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 16 ...

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... Protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Interruptible power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Real-time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 ST10F276E ...

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... ST10F276E 23.7.3 23.7.4 23.7.5 23.7.6 23.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 23.8.1 23.8.2 23.8.3 23.8.4 23.8.5 23.8.6 23.8.7 23.8.8 23.8.9 23.8.10 Jitter in the input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 23.8.11 Noise in the PLL loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 23.8.12 PLL lock/unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 23.8.13 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 23.8.14 32 kHz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 23 ...

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... Table 25. Flash non-volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 26. Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 27. Flash write operations Table 28. ST10F276E boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 29. ST10 configuration in BSL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 30. ST10 configuration in UART BSL mode (RS232 or K-line Table 31. ST10 configuration in CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 32. ...

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... ST10F276E Table 49. GPT2 timer input frequencies, resolutions and periods at 64 MHz Table 50. PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 88 Table 51. PWM unit frequencies and resolutions at 64 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 88 Table 52. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz Table 53 ...

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... Table 104. Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Table 105. Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 106. CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Table 107. External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Table 108. Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Table 109. Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 110. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Table 111. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 10/231 ST10F276E ...

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... Figure 7. Hardware provisions to activate the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 8. Memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 9. UART bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 10. Baud rate deviation between host and ST10F276E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 11. CAN bootstrap loader sequence Figure 12. Bit rate measurement over a predefined zero-frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 13. Reset boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 14. ...

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... Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Figure 51. Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Figure 52. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Figure 53. ST10F276E PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Figure 54. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Figure 55. 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Figure 56. External clock drive XTAL1 203 Figure 57 ...

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... Flash memory, on-chip high-speed RAM, and clock generation via PLL. ST10F276E is processed in 0.18µm CMOS technology. The MCU core and the logic is supplied with 1.8V on-chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5V. ...

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... Port5 channels. ● External Memory bus potential limitations on maximum speed and maximum capacitance load could be introduced (under evaluation): ST10F276E will probably not be able to address an external memory at 64MHz with 0 wait states (under evaluation). ● XPERCON register bit mapping modified according to new peripherals implementation (not fully compatible with ST10F269). ● ...

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... ST10F276E Figure 1. Logic symbol XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT V AREF V AGND ST10F276E NMI STBY READY ALE WRL Port 5 16-bit Introduction Port 0 16-bit Port 1 16-bit Port 2 16-bit Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit RPD 15/231 ...

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... ST10F276E ST10F276E 108 P0H.0 / AD8 107 P0L.7 / AD7 106 P0L.6 / AD6 105 P0L.5 / AD5 104 P0L.4 / AD4 103 P0L.3 / AD3 102 P0L.2 / AD2 101 P0L.1 / AD1 100 P0L.0 / AD0 VSTBY 98 ALE 97 READY 96 WR/WRL VSS 93 VDD 92 P4.7 / A23 / CAN2_TxD / SDA 91 P4.6 / A22 / CAN1_TxD / CAN2_TxD 90 P4 ...

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... ST10F276E Table 1. Pin description Symbol Pin Type I ... ... 5 O P6 I/O 9-16 I/O I ... ... I/O P8 I/O 14 I/O I/O 15 I/O I 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers ...

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... P2.7 CC7IO CAPCOM: CC7 capture input/compare output P2.8 CC8IO CAPCOM: CC8 capture input/compare output EX0IN Fast external interrupt 0 input ... ... ... P2.15 CC15IO CAPCOM: CC15 capture input/compare output EX7IN Fast external interrupt 7 input T7IN CAPCOM2: timer T7 count input ST10F276E Function ...

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... ST10F276E Table 1. Pin description (continued) Symbol Pin Type 65-70, I/O 73-80, I P3 P3.6 - P3.13, P3. I 15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 3 outputs can be configured as push-pull or open drain drivers ...

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... Address latch enable output. In case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines. ST10F276E Function ...

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... I External access enable pin. A low level applied to this pin during and after Reset forces the ST10F276E to start the program from the external memory space. A high level forces ST10F276E to start in the internal memory space. This pin is also used (when Stand-by mode is entered, that is ST10F276E under reset and main V ...

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... NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F276E to go into power down mode. If NMI is high and PWDCFG = ‘0’, when PWRDN is executed, the part will continue to run in normal mode ...

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... ST10F276E 3 Functional description The architecture of the ST10F276E combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F276E. Figure 3. Block diagram XFLASH 320 KB ...

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... Bank 0 contains also a reserved sector named test-Flash. 24/231 Control section HV and Ref. generator + Program/erase controller I-BUS interface Description ST10F276E XFLASH (Module X) Bank 3: 128 Kbyte program memory Bank 2: 192 Kbyte program memory X-BUS interface Addresses 0x00 0000 to 0x08 FFFF 512 Kbyte ...

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... ST10F276E Bank 1 contains 128 Kbyte of program memory or parameter divided in two sectors (64 Kbyte each). The XFLASH module is composed of two banks as well. Bank 2 contains 192 Kbyte of program memory divided in three sectors. Bank 3 contains 128 Kbyte of program memory or parameter divided in two sectors (64 Kbyte each). ...

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... FFFF 0x0007 0000 - 0x0007 FFFF 0x0008 0000 - 0x0008 FFFF 0x0009 0000 - 0x0009 FFFF 0x000A 0000 - 0x000A FFFF 0x000B 0000 - 0x000B FFFF 0x000C 0000 - 0x000C FFFF 0x000D 0000 - 0x000D FFFF Addresses Size 32-bit (I-BUS ST10F276E ST10 Bus size 16-bit (X-BUS) ...

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... ST10F276E Table 5. Control register interface Bank FCR1-0 Flash control registers 1-0 FDR1-0 Flash data registers 1-0 FAR Flash address registers FER Flash error register Flash non-volatile protection FNVWPXR X register Flash non-volatile protection FNVWPIR I register Flash non-volatile access FNVAPR0 protection register 0 Flash non-volatile access ...

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... Program or Erase Suspend these bits are automatically reset and the bank returns to read mode. After a Program or Erase Resume these bits are automatically set again. 28/231 FCR Reserved Function ST10F276E Reset value: 0000h BSY1 BSY0 LOCK Res. BSY3 BSY2 Res ...

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... ST10F276E Table 6. Flash control register 0 low (continued) Bit Flash registers access locked When this bit is set, it means that the access to the Flash Control Registers FCR0H/- FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read access to the registers will output invalid data (software trap 009Bh) and any write access will be ineffective ...

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... It is forbidden to set this bit if bit ERR of FER is high (the operation is not accepted also forbidden to start a new write (program or erase) operation (by setting WMS high) when bit SUSP of FCR0 is high. Resetting this bit by software has no effect. 30/231 Function ST10F276E ...

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... ST10F276E 4.3.3 Flash control register 1 low The Flash control register 1 low (FCR1L), together with Flash control register 1 high (FCR1H), is used to select the sectors to erase, or during any write operation to monitor the status of each sector of the module selected by SMOD bit of FCR0H. First diagram shows FCR1L meaning when SMOD = 0 ...

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... B3S B2S RS RS FCR B1S B0S RS RS Function Table 10. These bits are automatically reset at the end of a erase operation if Table 10. These bits are automatically reset at the end of a erase operation if ST10F276E Reset value: 0000h Reserved B3F1 B3F0 RS Reset value: 0000h Reserved ...

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... ST10F276E Table 10. Banks (BxS) and sectors (BxFy) status bits meaning ERR SUSP 4.3.5 Flash data register 0 low The Flash address registers (FARH/L) and the Flash data registers (FDR1H/L-FDR0H/L) are used during the program operations to store Flash Address in which to program and data to program. ...

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... These bits must be written with the address of the Flash location to program in the ADD(15:2) following operations: word program (32-bit) and double word program (64-bit). In double word program bit ADD2 must be written to ‘0’. 34/231 Function FCR Function FCR Function ST10F276E Reset value: FFFFh Reset value: 0000h Reserved ...

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... ST10F276E 4.3.10 Flash address register high FARH (0x0E 0012 Table 16. Flash address register high Bit Address 20:16 ADD(20:16) These bits must be written with the address of the Flash location to program in the following operations: word program and double word program. 4.3.11 Flash error register Flash error register, as well as all the other Flash registers, can be properly read only once LOCK bit of register FCR0L is low ...

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... These three bits are the binary coding of the number of wait states introduced by the XFLASH interface through the XBUS internal READY signal. Default value after reset is 1111, that is the wait states are set. The following recommendations for the WS(3:0) ST10F276E are hereafter reported: For f For f 36/231 ...

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... ST10F276E 4.4 Protection strategy The protection bits are stored in non-volatile Flash cells inside XFLASH module, that are read once at reset and stored in 7 Volatile registers. Before they are read from the non- volatile cells, all the available protections are forced active during reset. ...

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... Write Protection Bank 1 / Sectors 1-0 (IFLASH) W1P(1:0) These bits, if programmed at 0, disable any write access to the sectors of Bank 1 (IFLASH). 38/231 NVR Reserved Function NVR W0P9W0P8W0P7W0P6W0P5W0P4W0P3W0P2W0P1W0P0 Function NVR Reserved Function ST10F276E Delivery value: FFFFh W3P1W3P0 RW Delivery value: FFFFh Delivery value: FFFFh W1P1W1P0 ...

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... ST10F276E 4.4.6 Flash non-volatile access protection register 0 Due to ST10 architecture, the XFLASH is seen as external memory: this made impossible to access protect it from real external memory or internal RAM. FNVAPR0 (0x0E DFB8 Table 23. Flash non-volatile access protection register 0 Bit Access Protection This bit, if programmed at 0, disables any access (read/write) to data mapped inside ...

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... Fetching from IRAM 40/231 NVR Function Read IFLASH/ Read XFLASH/ Jump to Jump to IFLASH XFLASH Yes / Yes Yes / Yes No / Yes Yes / Yes No / Yes Yes / Yes ST10F276E Delivery value: FFFFh Table 26 summarizes all Read FLASH Write FLASH Registers Registers Yes Yes Yes No Yes ...

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... ST10F276E Table 26. Summary of access protection level (continued) Memory fetch source Fetching from XRAM Fetching from External Memory 4.4.10 Write protection The Flash modules have one level of Write Protections: each sector of each bank of each Flash Module can be Software Write Protected by programming at 0 the related bit WyPx of FNVWPXRH/L-FNVWPIRH/L registers ...

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... FCR0H|= 0x8000; /*Operation resume*/ Before resuming a suspended Erase, FCR1H/FCR1L must be read to check if the Erase is already completed (FCR1H = FCR1L = 0x0000 if Erase is complete). Original setup of Select Operation bits in FCR0H/L must be restored before the operation resume, otherwise the operation is aborted and bit RESER of FER is set. 42/231 ST10F276E ...

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... ST10F276E Erase suspend, program and resume A Sector Erase operation can be suspended in order to program (Word or Double Word) another sector. Example: Sector Erase of sector B3F1 of Bank 3 in XFLASH Module. FCR0H|= 0x0800;/*Set SER in FCR0H*/ FCR1H|= 0x0002;/*Set B3F1*/ FCR0H|= 0x8000;/*Operation start*/ Example: Sector Erase Suspend. ...

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... A summary of the available Flash Module Write Operations is shown in Table 27. Flash write operations Operation Word Program (32-bit) Double Word Program (64-bit) Sector Erase 44/231 Select bit Address and data FARL/FARH WPG FDR0L/FDR0H FARL/FARH DWPG FDR0L/FDR0H FDR1L/FDR1H SER FCR1L/FCR1H ST10F276E Table 27. Start bit WMS WMS WMS ...

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... ST10F276E Table 27. Flash write operations (continued) Operation Set Protection Program/Erase Suspend Select bit Address and data SPR FDR0L/FDR0H SUSP None Internal Flash memory Start bit WMS None 45/231 ...

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... Bootstrap loader 5 Bootstrap loader ST10F276E implements innovative boot capabilities in order to ● support a user defined bootstrap (see Alternate bootstrap loader); ● support bootstrap via UART or bootstrap via CAN for the standard bootstrap. 5.1 Selection among user-code, standard or alternate bootstrap The selection among user-code, standard bootstrap or alternate bootstrap is made by special combinations on Port0L[5 ...

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... Entering the standard bootstrap loader As with the old ST10 bootstrap mode, the ST10F276E enters BSL mode if pin P0L.4 is sampled low at the end of a hardware reset. In this case, the built-in bootstrap loader is activated independently of the selected bus mode. The bootstrap loader code is stored in a special Test-Flash ...

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... Bootstrap loader 5.2.2 ST10 configuration in BSL When the ST10F276E has entered BSL mode, the configuration shown in automatically set (values that deviate from the normal reset values are marked in bold). Table 29. ST10 configuration in BSL mode Function or register Watchdog Timer Register SYSCON Context Pointer CP ...

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... Other than after a normal reset the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Depending on the selected serial link (UART0 or CAN1), pin TxD0 or CAN1_TxD is configured as output, so the ST10F276E can return the acknowledge byte. Even if the internal IFLASH is enabled, a code cannot be executed from it. ...

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... ST10F276E is reset with P0L.4 low. After loading a preselected number of bytes, ST10F276E begins executing the downloaded program. 3. The first level user code runs on ST10F276E. Typically, this first level user code is another loader that downloads the application software into the ST10F276E. 4. The loaded application software is now running. ...

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... P0L.4 5.2.5 Memory configuration in bootstrap loader mode The configuration (that is, the accessibility) of the ST10F276E’s memory areas after reset in Bootstrap Loader mode differs from the standard case. Pin EA is evaluated when BSL mode is selected to enable or to not enable the external bus: ● ...

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... Flash area Data fetch from internal Flash area Note: As long as ST10F276E is in BSL, the user’s software should not try to execute code from the internal IFlash, as the fetches are redirected to the Test-Flash. 5.2.6 Loading the start-up code After the serial link initialization sequence (see following chapters), the BSL enters a loop to receive 32 bytes (boot via UART) or 128 bytes (boot via CAN) ...

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... Exiting bootstrap loader mode To execute a program in normal mode, the BSL mode must first be ST10F276E exits BSL mode at a software reset (level on P0L.4 is ignored hardware reset (P0L.4 must be high in this case). After the reset, the ST10F276E starts executing from location 00’0000 programmed via pin EA ...

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... Entering bootstrap via UART The ST10F276E enters BSL mode if pin P0L.4 is sampled low at the end of a hardware reset. In this case, the built-in bootstrap loader is activated independently of the selected bus mode. The bootstrap loader code is stored in a special Test-Flash; no part of the standard mask ROM or Flash memory area is required for this ...

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... BTYP field, bit 7 and 6, is set according to Port0 configuration. Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Pin TxD0 is configured as output, so the ST10F276E can return the acknowledge byte. Even if the internal IFLASH is enabled, a code cannot be executed from it ...

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... This process may go through several iterations or may directly execute the final application. In all cases the ST10F276E still runs in BSL mode, that is, with the watchdog timer disabled and limited access to the internal Flash area. All code fetches from the internal IFLASH area (01’ ...

Page 57

... ST10F276E Figure 10. Baud rate deviation between host and ST10F276E F B 2.5% B Low The minimum baud rate (B of timer T6, when measuring the zero byte, that is, it depends on the CPU clock. Using the maximum T6 count 2 standard baud rate in this case would be 1200 baud. Baud rates below overflow ...

Page 58

... Entering the CAN bootstrap loader The ST10F276E enters BSL mode if pin P0L.4 is sampled low at the end of a hardware reset. In this case, the built-in bootstrap loader is activated independently of the selected bus mode. The bootstrap loader code is stored in a special Test-Flash; no part of the standard mask ROM or Flash memory area is required for this ...

Page 59

... ST10F276E configured in order to send an acknowledge frame. The ST10F276E will not send this Message Object but the host can request it by sending a remote frame. The acknowledge frame is the following for the ST10F276E: – Standard identifier = E6h – DLC = 3h – Data0 = D5h, that is, generic acknowledge of the ST10 devices – ...

Page 60

... BTYP field, bit 7 and 6, is set according to Port0 configuration. Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Pin CAN1_TxD1 is configured as output, so the ST10F276E can return the identification frame. Even if the internal IFLASH is enabled, a code cannot be executed from it ...

Page 61

... This process may go through several iterations or may directly execute the final application. In all cases the ST10F276E still runs in BSL mode, that is, with the watchdog timer disabled and limited access to the internal Flash area. All code fetches from the internal Flash area (01’ ...

Page 62

... CPU clk cycle) ; Test if 5th stuff bit detected ; Stop timer ; here the 5th stuff bit is detected: ; PT0 = 29 Bit_Time (25D and 4R) th recessive bit is: PT0 = 58 x (BRP + Tseg1 + Tseg2) 8 ≤ Tseg1 + Tseg2 ≤ 25 464 BRP) ≤ PT0 ≤ 1450 BRP) ST10F276E ...

Page 63

... ST10F276E Table 32. BRP and PT0 values BRP The error coming from the measurement of the 29 bit is maximal for the smallest BRP value and the smallest number of ticks in PT0. Therefore: To improve precision, the aim is to have the smallest BRP so that the time quantum is the smallest possible ...

Page 64

... The content of the bit timing register is: 0x1640. This gives a sample point at 80%. Note: The (Re)Synchronization Jump Width is fixed to 2 time quanta. 5.4.7 Bootstrap via CAN After the bootstrap phase, the ST10F276E CAN module is configured as follows: ● The pin P4.6 is configured as output (the latch value is ‘1’ = recessive) to assume CAN1_TxD function. ● ...

Page 65

... ST10F276E 5.5 Comparing the old and the new bootstrap loader Table 33 and Table 34 only) bootstrap and the new one (boot via UART or CAN). 5.5.1 Software aspects As the CAN1 is needed, XPERCON register is configured by the bootstrap loader code and bit XPEN of SYSCON is set. However, as long as the EINIT instruction is not executed (and it is not in the bootstrap loader code), the settings can be modified ...

Page 66

... All ST10F276E XRAM and Xperipherals modules can be accessed if enabled in XPERCON register. Note: The alternate boot mode can be used to reprogram the whole content of the ST10F276E User Flash (except Block 0 in Bank 2, where the alternate boot is mapped into). 5.6.3 Interrupts The ST10 interrupt vector table is always mapped from address 00’0000h. ...

Page 67

... ST10F276E Even if the internal IFLASH is enabled, a code cannot be executed from it. As the XFlash is needed, XPERCON register is configured by the ABM loader code and bit XPEN of SYSCON is set. However, as long as the EINIT instruction is not executed (and it is not in the bootstrap loader code), the settings can be modified this, perform the following steps: 1 ...

Page 68

... Alternate boot user software aspects User defined alternate boot code must start at 09’0000h. A new SFR created on the ST10F276E indicates that the device is running in Alternate Boot Mode: Bit 5 of EMUCON (mapped at 0xFE0Ah) is set when the alternate boot is selected by the reset configuration. ...

Page 69

... Selective Bootstrap Loader to poll only RxD0 (no boot via CAN). ● 0xXX02 configures the Selective Bootstrap Loader to poll only CAN1_RxD (no boot via UART). ● Other values allow the ST10F276E to execute an endless loop into the Test-Flash. Bootstrap loader Function 69/231 ...

Page 70

... Yes (P0L[5..4] = ‘10’ not not Read 00’1FFCh 09’0000h Selective Bootstrap Loader Jump to Test-Flash Standard start No (P0L[5..4] = ‘11’) No (P0L[5..4] = ‘other config.’) ST test modes SW RESET Running from test Flash Std. Bootstrap Loader Jump to Test-Flash User Mode / User Flash Start at 00’0000h ST10F276E ...

Page 71

... SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F276E’s instructions can be executed in one instruction cycle which requires 31.25ns at 64 MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted ...

Page 72

... QX0 IDX Offset Register QX1 IDX Offset Register Interrupt Controller ST10 CPU 72/231 Operand signed/unsigned Multiplier Concatenation 32 Mux Sign Extend MRW Scaler 0h 08000h Repeat Unit Mux 40 MCW A 40-bit Signed Arithmetic Unit MSW Flags MAE Control Unit ST10F276E Operand Mux MAH MAL 40 8-bit Left/Right Shifter ...

Page 73

... ST10F276E 6.2 Instruction set summary Table 38 lists the instructions of the ST10F276E. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Table 38. Standard instruction set summary Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) ...

Page 74

... Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation ST10F276E Bytes ...

Page 75

... ST10F276E 6.3 MAC coprocessor specific instructions Table 39 lists the MAC instructions of the ST10F276E. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Note that all MAC instructions are encoded on 4 bytes. Table 39. MAC instruction set summary Mnemonic ...

Page 76

... The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register. 76/231 ST10F276E ...

Page 77

... When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F276E has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. ...

Page 78

... T1IE T1INT T7IR T7IE T7INT T8IR T8IE T8INT T2IR T2IE T2INT T3IR T3IE T3INT T4IR T4IE T4INT T5IR T5IE T5INT ST10F276E Vector Trap location number 00’0058h 16h 00’005Ch 17h 00’0060h 18h 00’0064h 19h 00’0068h 1Ah 00’006Ch 1Bh 00’0070h 1Ch 00’0074h 1Dh 00’ ...

Page 79

... ST10F276E Table 40. Interrupt sources (continued) Source of interrupt or PEC service request GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error PWM Channel 0...3 See paragraph 8 ...

Page 80

... CAN2 Interrupt I2C Receive I2C Transmit I2C Error SSC1 Receive SSC1 Transmit SSC1 Error ASC1 Receive ASC1 Transmit ASC1 Transmit Buffer ASC1 Error PLL Unlock / OWD PWM1 Channel 3...0 80/231 7 0 XIRxSEL[7: Flag[7:0] XIRxSEL[15: Enable[7: XP0INT ST10F276E XPxIC.XPxIR ( XP1INT XP2INT XP3INT ...

Page 81

... ST10F276E 8.2 Exception and error traps list Table 42 shows all of the possible exceptions or error conditions that can arise during run- time. Table 42. Trap priorities Exception condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow ...

Page 82

... Capture / compare (CAPCOM) units 9 Capture / compare (CAPCOM) units The ST10F276E has two 16-channel CAPCOM units which support generation and control of timing sequences channels with a maximum resolution of 125ns at 64 MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events ...

Page 83

... ST10F276E Table 43. Compare modes (continued) Compare modes Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer Mode 3 period is generated Double Register Two registers operate on one pin; pin toggles on each compare match; several compare events Mode per timer period are possible ...

Page 84

... MHz 625 kHz 400ns 0.8µs 1.6µs 26.2ms 52.4ms 104.8 ms 100b 101b 110b 128 256 512 312.5 kHz 156.25 kHz 78.125 kHz 39.1 kHz 3.2µs 6.4µs 12.8µs 209.7ms 419.4ms 838.9ms ST10F276E 111b 1024 25.6µs 1.678s ...

Page 85

... ST10F276E Table 47. GPT1 timer input frequencies, resolutions and periods at 64 MHz MHz CPU 000b Prescaler factor 8 Input frequency 8 MHz Resolution 125ns Period maximum 8.2ms Figure 17. Block diagram of GPT1 T2EUD CPU Clock T2IN CPU Clock T3IN T3EUD T4IN CPU Clock T4EUD Timer input selection T2I / T3I / T4I ...

Page 86

... ST10F276E 111b 512 12.8µs 838.9ms 111b 512 128 kHz 8.0µs 524.3ms ...

Page 87

... ST10F276E Figure 18. Block diagram of GPT2 T5EUD CPU Clock T5IN CAPIN T6IN CPU Clock T6EUD T5 2n n=2...9 GPT2 Timer T5 Mode Control Clear Capture GPT2 CAPREL T6 GPT2 Timer T6 Mode 2n n=2...9 Control General purpose timer unit U/D Interrupt Request Interrupt Request Reload Interrupt Request ...

Page 88

... PWM modules 11 PWM modules Two pulse width modulation modules are available on ST10F276E: standard PWM0 and XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned or centre-aligned PWM. In addition, the PWM modules can generate PWM burst signals and single shot outputs. ...

Page 89

... I/O’s special features 12.2.1 Open drain mode Some of the I/O ports of ST10F276E support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND wired logical function. This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections), and is controlled through the respective Open Drain Control Registers ODPx ...

Page 90

... Parallel ports 12.2.2 Input threshold control The standard inputs of the ST10F276E determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds ...

Page 91

... ST10F276E This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in the multiplexed external bus modes of PORT0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data ...

Page 92

... The ST10F276E has 16+8 multiplexed input channels on Port 5 and Port 1. The selection between Port 5 and Port 1 is made via a bit in a XBus register. Refer to the user manual for a detailed description. ...

Page 93

... ST10F276E register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer. ● Wait for ADDAT read mode: When using continuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the ADWR bit of ADCON control register must be activated ...

Page 94

... SSC1 (XBUS mapped). 14.1 Asynchronous / synchronous serial interfaces The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial communication between the ST10F276E and other microcontrollers, microprocessors or external peripherals. 14.2 ASCx in asynchronous mode In asynchronous mode 9-bit data transfer, parity generation and the number of stop bits can be selected ...

Page 95

... The deviation errors given in the errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency). 14.3 ASCx in synchronous mode In synchronous mode, data is transmitted or received synchronously to a shift clock which is generated by the ST10F276E. Half-duplex communication baud (at 40 MHz possible in this mode. CPU Table 54. ...

Page 96

... High speed synchronous serial interfaces The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible high- speed serial communication between the ST10F276E and other microcontrollers, microprocessors or external peripherals. The SSCx supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSCx itself (master mode received from an external master (slave mode) ...

Page 97

... ST10F276E Table 56. Synchronous baud rate and reload values (f Reserved Can be used only with f 6.6M Baud 5M Baud 2.5M Baud 1M Baud 100K Baud 10K Baud 1K Baud 306 Baud Table 57. Synchronous baud rate and reload values (f Reserved Can be used only with f Can be used only with f ...

Page 98

... C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O controlled by P4, DP4 and ODP4. The speed of the I 2 Fast I C mode (100 to 400 kHz). 98/231 2 C Bus specification. The bus modes are supported interface may be selected between Standard mode (0 to 100 kHz) and ST10F276E 2 C Module can ...

Page 99

... ST10F276E 16 CAN modules The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active based on the C-CAN specification. Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers ...

Page 100

... CAN bus configurations Depending on application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F276E is able to support these two cases. Single CAN bus The single CAN Bus multiple interfaces configuration may be implemented using two CAN transceivers as shown in Figure 20 ...

Page 101

... ST10F276E Multiple CAN bus The ST10F276E provides two CAN interfaces to support such kind of bus configuration as shown in Figure 22. Figure 22. Connection to two different CAN buses (e.g. for gateway application) CAN_H CAN_L Parallel Mode In addition to previous configurations, a parallel mode is supported. This is shown in Figure 23. ...

Page 102

... Vice versa, when at power on and after Reset, the 32 kHz is not present, the main STBY oscillator drives the RTC counter, and since it is powered by the main power supply, it cannot be maintained running in Stand-by mode, while in Power Down mode the main oscillator is maintained running to provide the reference to the RTC module (if not disabled). 102/231 ST10F276E ...

Page 103

... ST10F276E 18 Watchdog timer The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. ...

Page 104

... Power-on (1) Low t > RSTIN LHWR High t > (1032 + 12) TCL + max(4 TCL, 500ns) RSTIN t > max(4 TCL, 500ns) RSTIN SHWR High t < (1032 + 12) TCL + max(4 TCL, 500ns) RSTIN (3) WDTR WDT overflow (3) SWR SRST instruction execution ST10F276E Table 60. Conditions (2) (2) 19.5 and 19.6). ...

Page 105

... ST10F276E does not need a stabilized clock signal to detect an asynchronous reset suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the RPD pin must be held at low level until the device clock signal is stabilized and the system configuration value on Port0 is settled ...

Page 106

... Ampere, so the current shall be limited by the external hardware. The limit of current is imposed by power dissipation considerations (Refer to Chapter 23: Electrical characteristics). and 25 Asynchronous Power-on timing diagrams are reported, ST10F276E pin should 18 ...

Page 107

... ST10F276E Figure 24. Asynchronous power-on RESET ( XTAL1 RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST ≤ 1.2 ms (for resonator oscillation + PLL stabilization) ≤ 10.2 ms (for crystal oscillation + PLL stabilization) ≥ (for on-chip VREG stabilization) ≤ 2 TCL ... ≥ ≤ 500 ns 3 ...

Page 108

... PLL stabilization) ≥ (for on-chip VREG stabilization) (1) 3..8 TCL ... ≥ ≤ 500 ns 3..4 TCL transparent transparent not transparent Latching point of Port0 for system start-up configuration Section 19.7: Reset circuitry and figures 37, ST10F276E not t. not t. not t. 8 TCL 38 ...

Page 109

... ST10F276E Figure 26. Asynchronous hardware RESET ( RPD RSTIN RSTF (after filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (internal) FLARST RST 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed); longer than 500ns to take into account input filter on RSTIN pin (1) ≥ ≤ 500 ns ≥ ...

Page 110

... Flash is used, the restarting occurs after the embedded Flash initialization routine is completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F276E starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine ...

Page 111

... Flash initialization when (internal memory selected). Then, the code execution restarts. The system configuration is latched from Port0, and ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F276E starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine ...

Page 112

... TCL 8 TCL µ 200 A Discharge Section 19.1 ST10F276E ≤ 2 TCL not t. not t. 7 TCL ≤ this time RSTF is sampled HIGH or LOW SHORT or LONG reset 2) V > 2.5V Asynchronous Reset not entered RPD ...

Page 113

... ST10F276E BDRSTEN is cleared after reset. 4. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Figure 29. Synchronous short / long hardware RESET ( ≤4 TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] ...

Page 114

... TCL At this time RSTF is sampled LOW definitely LONG reset µ 200 A Discharge Section 19.1). ST10F276E ≤ 2 TCL 3..4 TCL not t. not t. not t. 7 TCL ≤ > 2.5V Asynchronous Reset not entered RPD ...

Page 115

... ST10F276E Figure 31. Synchronous long hardware RESET ( TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST RSTOUT RPD 1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. ...

Page 116

... Figure 32 WDT unidirectional RESET ( RSTIN P0[15:13] P0[12:8] P0[7:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT 116/231 and Figure 33 for unidirectional SW reset timing, and to figures 34, not transparent transparent not transparent not transparent 1024 TCL ST10F276E ≤ 2 TCL not t. not t. 7 TCL ≤ ...

Page 117

... ST10F276E Figure 33 WDT unidirectional RESET ( RSTIN P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 19.6 Bidirectional reset As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization routine, until the protected EINIT instruction (End of Initialization) is completed ...

Page 118

... Flash itself extend the internal reset duration well beyond the filter delay. Figures 34, 35 and reset events: In particular, 118/231 36 summarize the timing for Software and Watchdog Timer Bidirectional Figure 36 shows the degeneration into Hardware reset. ST10F276E ...

Page 119

... ST10F276E Figure 34 WDT bidirectional RESET ( RSTIN RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT ≥ ≥ ≤ 500 ns ≤ 500 ns not transparent transparent not transparent not transparent ≤ 1024 TCL System reset not t. not t. ≤ 2 TCL 7 TCL ...

Page 120

... Figure 35 WDT bidirectional RESET ( RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 120/231 ≥ ≤ 500 ns not transparent not t. transparent not transparent not t. not transparent 1024 TCL At this time RSTF is sampled HIGH WDT Reset is flagged in WDTCON ST10F276E 8 TCL ...

Page 121

... If bit PWDCFG of SYSCON register is set, an internal pull-up resistor is activated at the end of the reset sequence. This pull-up will charge any capacitor connected on RPD pin. The simplest way to reset the ST10F276E is to insert a capacitor C1 between RSTIN pin and V , and a capacitor between RPD pin and V ...

Page 122

... This mechanism insures recovery from very catastrophic failure. Figure 37. Minimum external reset circuitry The minimum reset circuit of the ST10F276E itself during software or watchdog triggered resets, because of the capacitor C1 that will keep the voltage on RSTIN pin above V reset sequence, and thus will trigger an asynchronous reset sequence. Figure 38 shows an example of a reset circuit ...

Page 123

... ST10F276E Figure 38. System reset circuit ST10F276 Figure 39. Internal (simplified) reset circuitry Internal Reset Signal External Hardware RSTIN o.d. R0 Open Drain Inverter RPD + C0 EINIT Instruction Clr Q Set Reset State Machine Clock SRST instruction Trigger watchdog overflow Clr Reset Sequence (512 CPU Clock Cycles) ...

Page 124

... Next two timing diagrams bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to external circuit scheme). Figure 40. Example of software or watchdog bidirectional reset ( 124/231 (Figure 40 and Figure 41) provides additional examples of ST10F276E Figure 38 for the ...

Page 125

... ST10F276E Figure 41. Example of software or watchdog bidirectional reset ( System reset 125/231 ...

Page 126

... Activated by internal logic for 1024 TCL 1032 + 12 TCL + max(4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) Activated by internal logic only for 1024 TCL 1032 + 12 TCL + max(4 TCL, 500ns) Activated by internal logic only for 1024 TCL ST10F276E WDTCON flags - ...

Page 127

... ST10F276E Table 61. Reset event (continued) Event Synch Synch. (2) Software Reset Synch Synch Synch Synch. (2) Watchdog Reset Synch Synch can degenerate into a Long Hardware Reset and consequently differently flagged (see 2. When Bidirectional is active (and with RPD=0), it can be followed by a Short Hardware Reset and consequently differently flagged (see for details) ...

Page 128

... H.1 H.0 L.7 SALSEL CSSEL WRC BUSTYP CSSEL WRC SALSEL Port 4 Port 6 Logic Logic P0L.7 SYSCON WRCFG 7 10 L.6 L.5 L.4 L.3 L.2 L.1 BSL Res. ADP EMU Bootstrap Loader Internal Control Logic 2 BUSCON0 BUS ALE BTYP ACT0 CTL0 ST10F276E L VSTBY ...

Page 129

... Power reduction modes Three different power reduction modes with different levels of power reduction have been implemented in the ST10F276E. In Idle mode only CPU is stopped, while peripheral still operate. In Power Down mode both CPU and peripherals are stopped. In Stand-by mode the main power supply (V ...

Page 130

... A dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1.65V in Stand-by mode) to bias all those circuits that shall remain active: the portion of XRAM (16 Kbytes for ST10F276E), the RTC counters and 32 kHz on- chip oscillator amplifier. 130/231 ...

Page 131

... V 18SB from ST10F276E Core (active low signal) is low enough to be recognized as a logic “0” by the RAM interface (due to V address for the RAM and an unwanted data corruption could occur. For this reason, an extra interface, powered by the switched supply, is used to prevent the RAM from this kind of potential corruption mechanism ...

Page 132

... Being the main oscillator powered by V oscillator is stopped. 132/231 without any glitch, in order to avoid spurious exiting from reset status with unstable power supply. STBY pin external voltage). becomes higher than about 1.0V, there 18 ), the Real-Time Clock DD , once this is switched off, the DD ST10F276E is DD ...

Page 133

... ST10F276E 20.3.4 Power reduction modes summary Table 63 summarizes the different Power reduction modes. Table 63. Power reduction modes summary Mode Idle Power Down Stand- off off off off on on off off on on off off off on off off off on off off Power reduction modes ...

Page 134

... SYSCON possible to program the clock prescaling factor: in this way on P3.15 a prescaled value of the CPU clock can be output. When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15 does not output any clock signal, even though XCLKOUTDIV register is programmed. 134/231 ST10F276E ...

Page 135

... Register set 22.1 Introduction This section summarizes all registers implemented in the ST10F276E and explains the description format used in the chapters to describe the function and layout of the SFRs. For easy reference, the registers (except for GPRs) are sorted in two ways: – Sorted by address, to check which register is referenced by a given address. ...

Page 136

... CPU general purpose (byte) register RL0 F1h CPU general purpose (byte) register RH0 F2h CPU general purpose (byte) register RL1 F3h CPU general purpose (byte) register RH1 F4h CPU general purpose (byte) register RL2 ST10F276E Reset value UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh ...

Page 137

... ST10F276E Table 66. General purpose registers (GPRs) bytewise addressing (continued) Physical Name address RL0 (CP RH2 (CP RL3 (CP RH3 (CP RL4 (CP RH4 (CP RL5 (CP RH5 (CP RL6 (CP RH6 (CP RL7 (CP RH7 (CP 8-bit Description address F0h CPU general purpose (byte) register RL0 F5h CPU general purpose (byte) register RH2 ...

Page 138

... Special function registers ordered by name Table 67 lists in alphabetical order all SFRs which are implemented in the ST10F276E. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “ ...

Page 139

... ST10F276E Table 67. Special function registers ordered by address (continued) Physical Name address CC15 FE9Eh CC15IC b FF96h CC16 FE60h CC16IC b F160hE CC17 FE62h CC17IC b F162hE CC18 FE64h CC18IC b F164hE CC19 FE66h CC19IC b F166hE CC1IC b FF7Ah CC2 FE84h CC20 FE68h CC20IC b F168hE CC21 FE6Ah ...

Page 140

... P0H direction control register 80h P0L direction control register 83h P1H direction control register 82h P1L direction control register E1h Port 2 direction control register E3h Port 3 direction control register ST10F276E Reset value 0000h - - 00h 0000h - - 00h - - 00h 0000h - - 00h 0000h - - 00h ...

Page 141

... ST10F276E Table 67. Special function registers ordered by address (continued) Physical Name address DP4 b FFCAh DP6 b FFCEh DP7 b FFD2h DP8 b FFD6h DPP0 FE00h DPP1 FE02h DPP2 FE04h DPP3 FE06h EMUCON FE0Ah EXICON b F1C0hE EXISEL b F1DAhE IDCHIP F07ChE IDMANUF F07EhE IDMEM F07AhE IDPROG F078hE ...

Page 142

... PWM module pulse width register 0 19h PWM module pulse width register 1 1Ah PWM module pulse width register 2 1Bh PWM module pulse width register 3 98h PWM module control register 0 99h PWM module control register 1 ST10F276E Reset value - - 00h - - 00h 0000h 0000h - - 00h XXXXh 0000h - - 00h ...

Page 143

... ST10F276E Table 67. Special function registers ordered by address (continued) Physical Name address PWMIC b F17EhE QR0 F004hE QR1 F006hE QX0 F000hE QX1 F002hE RP0Hb F108hE S0BG FEB4h S0CON b FFB0h S0EIC b FF70h S0RBUF FEB2h S0RIC b FF6Eh S0TBIC b F19ChE S0TBUF FEB0h S0TIC b FF6Ch SP FE12h SSCBR ...

Page 144

... See Section 8.1 C7h See Section 8.1 CBh See Section 8.1 CFh See Section 8.1 12h XPER configuration register 8Eh Constant value 0’s register (read-only) ST10F276E Reset value 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h ...

Page 145

... Special function registers ordered by address Table 68 lists by order of their physical addresses all SFRs which are implemented in the ST10F276E. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “ ...

Page 146

... C7h See Section 8.1 CAh CAPCOM register 31 interrupt control register CBh See Section 8.1 Serial channel 0 transmit buffer interrupt control CEh register. CFh See Section 8.1 ST10F276E Reset value 0000h 0000h XXXXh 0000h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h - - 00h ...

Page 147

... ST10F276E Table 68. Special function registers ordered by address (continued) Physical Name address EXICON b F1C0hE ODP2 b F1C2hE PICON b F1C4hE ODP3 b F1C6hE ODP4 b F1CAhE ODP6 b F1CEhE ODP7 b F1D2hE ODP8 b F1D6hE EXISEL b F1DAhE DPP0 FE00h DPP1 FE02h DPP2 FE04h DPP3 FE06h CSP FE08h EMUCON FE0Ah ...

Page 148

... CAPCOM register 3 44h CAPCOM register 4 45h CAPCOM register 5 46h CAPCOM register 6 47h CAPCOM register 7 48h CAPCOM register 8 49h CAPCOM register 9 4Ah CAPCOM register 10 ST10F276E Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...

Page 149

... ST10F276E Table 68. Special function registers ordered by address (continued) Physical Name address CC11 FE96h CC12 FE98h CC13 FE9Ah CC14 FE9Ch CC15 FE9Eh ADDAT FEA0h WDT FEAEh S0TBUF FEB0h S0RBUF FEB2h S0BG FEB4h PECC0 FEC0h PECC1 FEC2h PECC2 FEC4h PECC3 FEC6h PECC4 FEC8h ...

Page 150

... BBh SSC error interrupt control register BCh CAPCOM register 0 interrupt control register BDh CAPCOM register 1 interrupt control register BEh CAPCOM register 2 interrupt control register BFh CAPCOM register 3 interrupt control register ST10F276E Reset value FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...

Page 151

... ST10F276E Table 68. Special function registers ordered by address (continued) Physical Name address CC4IC b FF80h CC5IC b FF82h CC6IC b FF84h CC7IC b FF86h CC8IC b FF88h CC9IC b FF8Ah CC10IC b FF8Ch CC11IC b FF8Eh CC12IC b FF90h CC13IC b FF92h CC14IC b FF94h CC15IC b FF96h ADCIC b FF98h ADEIC b FF9Ah T0IC b FF9Ch ...

Page 152

... X-registers sorted by name Table 69 lists by order of their names all X-Bus registers which are implemented in the ST10F276E. Although also physically mapped on X-Bus memory space, the Flash control registers are listed in a separate section. Note: The X-registers are not bit-addressable. Table 69. ...

Page 153

... ST10F276E Table 69. X-Registers ordered by name (continued) Name CAN1IF2DA2 CAN1IF2DB1 CAN1IF2DB2 CAN1IF2M1 CAN1IF2M2 CAN1IF2MC CAN1IP1 CAN1IP2 CAN1IR CAN1MV1 CAN1MV2 CAN1ND1 CAN1ND2 CAN1SR CAN1TR CAN1TR1 CAN1TR2 CAN2BRPER CAN2BTR CAN2CR CAN2EC CAN2IF1A1 CAN2IF1A2 CAN2IF1CM CAN2IF1CR CAN2IF1DA1 CAN2IF1DA2 CAN2IF1DB1 CAN2IF1DB2 CAN2IF1M1 CAN2IF1M2 CAN2IF1MC CAN2IF2A1 CAN2IF2A2 ...

Page 154

... RTC Alarm register high byte ED12h RTC Alarm register low byte ED00H RTC Control register ED0Ch RTC Divider counter high byte ED0Ah RTC Divider counter low byte ED10h RTC Programmable counter high byte ST10F276E Description Reset value 0000h 0001h 0000h 0000h 0000h 0000h FFFFh FFFFh ...

Page 155

... ST10F276E Table 69. X-Registers ordered by name (continued) Name RTCL RTCPH RTCPL XCLKOUTDIV XEMU0 XEMU1 XEMU2 XEMU3 XIR0CLR XIR0SEL XIR0SET XIR1CLR XIR1SEL XIR1SET XIR2CLR XIR2SEL XIR2SET XIR3CLR XIR3SEL XIR3SET XMISC XP1DIDIS XPEREMU XPICON XPOLAR XPP0 XPP1 XPP2 XPP3 XPT0 XPT1 XPT2 Physical address ...

Page 156

... XSSC control register E804h XSSC clear control register (write-only) E802h XSSC set control register (write-only) E880h XSSC port control register E808h XSSC receive buffer E806h XSSC transmit buffer ST10F276E Description Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...

Page 157

... X-registers ordered by address Table 70 lists by order of their physical addresses all X-Bus registers which are implemented in the ST10F276E. Although also physically mapped on X-Bus memory space, the Flash control registers are listed in a separate section. Note: The X-registers are not bit-addressable. Table 70. ...

Page 158

... XPWM module up/down counter 3 EC20h XPWM module period register 0 EC22h XPWM module period register 1 EC24h XPWM module period register 2 EC26h XPWM module period register 3 EC30h XPWM module pulse width register 0 ST10F276E Description Reset value - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...

Page 159

... ST10F276E Table 70. X-registers ordered by address (continued) Name XPW1 XPW2 XPW3 XPWMPORT RTCCON RTCPL RTCPH RTCDL RTCDH RTCL RTCH RTCAL RTCAH CAN2CR CAN2SR CAN2EC CAN2BTR CAN2IR CAN2TR CAN2BRPER CAN2IF1CR CAN2IF1CM CAN2IF1M1 CAN2IF1M2 CAN2IF1A1 CAN2IF1A2 CAN2IF1MC CAN2IF1DA1 CAN2IF1DA2 CAN2IF1DB1 CAN2IF1DB2 CAN2IF2CR CAN2IF2CM CAN2IF2M1 ...

Page 160

... CAN1: IF1 arbitration 2 EF1Ch CAN1: IF1 message control EF1Eh CAN1: IF1 data A 1 EF20h CAN1: IF1 data A 2 EF22h CAN1: IF1 data B 1 EF24h CAN1: IF1 data B 2 ST10F276E Description Reset value FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...

Page 161

... ST10F276E Table 70. X-registers ordered by address (continued) Name CAN1IF2CR CAN1IF2CM CAN1IF2M1 CAN1IF2M2 CAN1IF2A1 CAN1IF2A2 CAN1IF2MC CAN1IF2DA1 CAN1IF2DA2 CAN1IF2DB1 CAN1IF2DB2 CAN1TR1 CAN1TR2 CAN1ND1 CAN1ND2 CAN1IP1 CAN1IP2 CAN1MV1 CAN1MV2 Physical address EF40h CAN1: IF2 command request EF42h CAN1: IF2 command mask EF44h CAN1: IF2 mask 1 ...

Page 162

... Register set 22.8 Flash registers ordered by name Table 71 lists by order of their names all Flash control registers which are implemented in the ST10F276E. Note that as they are physically mapped on the X-Bus, these registers are not bit-addressable. Table 71. Flash registers ordered by name Name FARH ...

Page 163

... ST10F276E 22.9 Flash registers ordered by address Table 72 lists by order of their physical addresses all Flash control registers which are implemented in the ST10F276E. Note that as they are physically mapped on the X-Bus, these registers are not bit-addressable. Table 72. Flash registers ordered by address Name FCR0L ...

Page 164

... Register set 22.10 Identification registers The ST10F276E has four Identification registers, mapped in ESFR space. These registers contain: ● the manufacturer identifier ● the chip identifier with revision number ● the internal Flash and size identifier ● the programming voltage description IDMANUF (F07Eh / 3Fh) ...

Page 165

... IDPROG description Bit Programming VDD voltage PROGVDD VDD voltage when programming EPROM or Flash devices is calculated using the following formula: VDD = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F276E (5V). PROGVPP Programming VPP voltage (no need of external VPP) - 00h Note: All identification words are read-only registers. ...

Page 166

... Register set 22.11 System configuration registers The ST10F276E has registers used for a different configuration of the overall system. These registers are described below. SYSCON (FF12h / 89h ROM STKSZ Note: SYSCON Reset Value is: 0000 0xx0 0x00 0000b Table 77. SYSCON description Bit XBUS peripheral share mode control 0: External accesses to XBUS peripherals are disabled ...

Page 167

... ST10F276E Table 77. SYSCON description (continued) Bit Write configuration control (inverted copy of WRC bit of RP0H) WRCFG 0: Pins WR and BHE retain their normal function. 1: Pin WR acts as WRL, pin BHE acts as WRH. System clock output enable (CLKOUT) 0: CLKOUT disabled, pin may be used for general purpose I/O. ...

Page 168

... The CS signal is generated for the duration of the read command. Write chip select enable CSWENx 0: The CS signal is independent of the write command (WR, WRL, WRH). 1: The CS signal is generated for the duration of the write command. 168/231 SFR BUSACT4 ALECTL4 - Function ST10F276E Reset value: 0000h BTYP MTTC4 RWDC4 MCTC ...

Page 169

... ST10F276E Note: 1 BTYP (bit 6 and 7) is set according to the configuration of the bit l6 and l7 of PORT0 latched at the end of the reset sequence. 2 BUSCON0 is initialized with 0000h pin is high during reset pin is low during reset, bit BUSACT0 and ALECTRL0 are set (‘1’) and bit field BTYP is loaded with the bus configuration selected via PORT0 ...

Page 170

... XP3IR XP3IE RW SFR area xxIR xxIE RW Function Reset value: 0000h EXI2SS EXI1SS Function Alternate source CAN1_RxD CAN2_RxD / SCL RTCSI (Second) RTCAI (Alarm) Not used (zero) Reset value: --00h XP3ILVL RW RW Reset value: --00h ILVL RW RW ST10F276E 1 0 EXI0SS GLVL GLVL RW ...

Page 171

... ST10F276E Table 83. SFR area description Bit Group level Defines the internal order for simultaneous requests of the same priority. GLVL 3: Highest group priority 0: Lowest group priority Interrupt priority level Defines the priority level for the arbitration of requests. ILVL Fh: Highest priority level 0h: Lowest priority level ...

Page 172

... ADDRSELx register. All pins used for X-Peripherals can be used as General Purpose I/O whenever the related module is not enabled. 172/231 2 C enable bit 2 C are disabled, external access performed. Address enabled and can be accessed XPWM and the XBUS Additional Features are Function ST10F276E ...

Page 173

... ST10F276E The default XPER selection after Reset is such that CAN1 is enabled, CAN2 is disabled, XRAM1 (2 Kbyte XRAM) is enabled and XRAM2 (64 Kbyte XRAM) is disabled; all the other X-Peripherals are disabled after Reset. Register XPERCON cannot be changed after the global enabling of X-Peripherals, that is, after setting of bit XPEN in SYSCON register ...

Page 174

... Four additional registers are implemented for emulation purposes only. Similarly to XPEREMU, they are write-only registers. XEMU0 (EB76h XEMU1 (EB78h XEMU2 (EB7Ah XEMU3 (EB7Ch 174/231 XBUS XEMU0(15:0) W XBUS XEMU1(15:0) W XBUS XEMU2(15:0) W XBUS XEMU3(15:0) W ST10F276E Reset value: xxxxh Reset value: xxxxh Reset value: xxxxh Reset value: xxxxh ...

Page 175

... ST10F276E 23 Electrical characteristics 23.1 Absolute maximum ratings Table 86. Absolute maximum ratings Symbol V Voltage Voltage on V STBY V Voltage on V AREF V Voltage on V AGND V Voltage on any pin with respect to ground ( Input current on any pin during overload condition OV I Absolute sum of all input currents during overload condition ...

Page 176

... V , expressed in Watt. This is the Chip Internal Power < which may be ignored. On the other hand, P I/O INT and 273°C) ( 273°C) + Θ Using this value of K, the values Description Section 23. ( neglected) is given by Value (typical ST10F276E may I/O and Unit °C/W ...

Page 177

... LQFP 144 23.4 Parameter interpretation The parameters listed in the following tables represent the characteristics of the ST10F276E and its demands on the system. Where the ST10F276E logic provides signals with their respective timing characteristics, the symbol “CC” (Controller Characteristics) is included in the “Symbol” column. Where the external system must provide signals with their respective timing characteristics to the ST10F276E, the symbol “ ...

Page 178

... OH2 750 µA OH2 150 µA OH2 (2) (3) (4) (5) (3) (4)(5) 100 kΩ nominal (6)( 2.4 V OUT (6)( 0.4V OUT (6)( 0.4V OUT ST10F276E Limit values Min. Max. 400 700 750 1400 750 1400 0 50 400 700 500 1500 0.4 - 0.05 0 0.5 V ...

Page 179

... ST10F276E Table 90. DC characteristics (continued) Symbol Parameter (6)(8) I ALE active current ALEH Port 6 inactive current I (6)(7) P6H (P6[4:0]) I Port 6 active current (P6[4:0]) P6L (6) I P0H PORT0 configuration current (7) I P0L C CC Pin capacitance (digital inputs / outputs) IO Run mode power supply current ...

Page 180

... Alternate Data Input Latch Fast External Interrupt Input Flash Sense Amplifier and Column Decoder For Port2 complete structure refer also to is expressed in MHz). This dependency is is expressed in MHz). This dependency is is expressed in MHz). This dependency is P2.0 CC0IO Output Buffer Test Mode Figure 44. ST10F276E - DD ...

Page 181

... ST10F276E Figure 45. Supply current versus the operating frequency (RUN and IDLE modes) 150 100 23.6 Flash characteristics = 5V ± 10 Table 91. Flash characteristics Parameter (2) Word program (32-bit) (2) Double word program (64-bit) Bank 0 program (384 Kbyte) (double word program) Bank 1 program (128 Kbyte) (double word program) ...

Page 182

... Kbyte (code store) > 20 years - - - ST10F276E Unit Notes 100k cycles 28.6 not preprogrammed s 26.1 preprogrammed 9.8 not preprogrammed s 9.0 preprogrammed 14.5 not preprogrammed s 13.3 preprogrammed 9.8 not preprogrammed s 9.0 preprogrammed 38 ...

Page 183

... ST10F276E 1. Two 64 Kbyte Flash sectors may be typically used to emulate Kbytes of EEPROM. Therefore, in case of an emulation Kbyte EEPROM, 100000 Flash Program / Erase cycles are equivalent to 800000 EEPROM Program/Erase cycles. For an efficient use of the Read While Write feature and/or EEPROM Emulation please refer to dedicated application note AN2061 - EEPROM Emulation with ST10F2xx ...

Page 184

... The AIN , changes of the analog input voltage have no effect on the conversion S depend on programming and can be taken from S , the time for determining the digital result and the time to load S Table 94. ST10F276E ≤ AREF DD Limit values Min. Max. 4.5 V ...

Page 185

... The time that the two different actions take during conversion (sampling and converting) can be programmed within a certain range in the ST10F276E relative to the CPU clock. The absolute time consumed by the different conversion steps is therefore independent from the general speed of the controller ...

Page 186

... TCL * 560 TCL * 480 TCL * 960 TCL * 560 TCL * 1120 TCL * 800 TCL * 1120 TCL * 1600 TCL * 1120 ) and converts it into 10-bit digital data. The AREF ST10F276E Extra Total conversion TCL * 52 TCL * 532 TCL * 44 TCL * 724 TCL * 52 TCL * 772 TCL * 28 TCL * 868 ...

Page 187

... ST10F276E Nonlinearity error Nonlinearity error is the deviation between actual and the best-fitting A/D conversion charac- teristics (see Figure – Differential nonlinearity error is the actual step dimension versus the ideal one (1 LSB IDEAL – Integral nonlinearity error is the distance between the center of the actual step and the center of the bisector line, in the actual characteristics ...

Page 188

... S R Filter resistance F C Filter capacitance F R Current limiter resistance L R Channel selection switch impedance SW R Sampling switch impedance AD c Pin capacitance (two contributions, CP1 and CP2 Sampling capacitance S ST10F276E and recommended in AREF AGND INTERNAL CIRCUIT SCHEME V DD Channel Sampling Selection ...

Page 189

... ST10F276E Input leakage and external circuit The series resistor utilized to limit the current to a pin (see R with a large source impedance, can lead to a degradation of A/D converter accuracy when input leakage is present. Data about maximum input leakage current at each pin is provided in characteristics. Input leakage is greatest at high operating temperatures and in general decreases by one half for each 10° ...

Page 190

... constraint ≤ (filter resistance). Being that C F (at the end of the A2 . The following equation must be A1 already charged ⋅ the filter is very high with longer than the sampling time C ST10F276E to the P2 and P is always must be at ...

Page 191

... ST10F276E time constant of the filter R charge level on C the sampling switch is closed. Figure 49. Anti-aliasing filter and conversion rate Analog source bandwidth ( Anti-aliasing filter ( The considerations above lead to impose new constraints to the external circuit, to reduce the accuracy error due to the voltage drop on C ...

Page 192

... S ): 500Ω 200Ω ----------- - = = 15.9µ 2π and C and taking some margin (4000 instead of 2048 ⋅ 4000 16nF = = ≅ = ------------------- - = 995Ω 1kΩ R π 4kΩ ------------ - INJ : 2.9kΩ R ------------ - R R – – INJ , C and 10MΩ -------------- - ST10F276E are defined. Some conditions L ...

Page 193

... V The other conditions to verify are if the time constants of the transients are really and significantly shorter than the sampling period duration T For a complete set of parameters characterizing the ST10F276E A/D converter equivalent circuit, refer to Table 93: A/D converter characteristics on page 23 ...

Page 194

... Electrical characteristics 23.8.2 Definition of internal timing The internal operation of the ST10F276E is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “ ...

Page 195

... ST10F276E 23.8.3 Clock generation modes Table 95 associates the combinations of these 3 bits with the respective clock generation mode. Table 95. On-chip clock generator selections P0.15-13 CPU frequency (P0H.7-5) f CPU XTAL XTAL XTAL XTAL XTAL XTAL XTAL XTAL 1. The external clock input range refers to a CPU clock range of 1...64 MHz. Moreover, the PLL usage is limited to 4-12 MHz input frequency range. All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the internal oscillator amplifier (apart from Direct Drive) ...

Page 196

... Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. 23.8.6 Oscillator watchdog (OWD) An on-chip watchdog oscillator is implemented in the ST10F276E. This feature is used for safety operation with an external crystal oscillator (available only when using direct drive mode with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the frequency of the external crystal oscillator) ...

Page 197

... PLL jitter is negligible. Refer to 23.8.8 Voltage controlled oscillator The ST10F276E implements a PLL which combines different levels of frequency dividers with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. presents a detailed summary of the internal settings and VCO frequency. Table 96. ...

Page 198

... VCO circuitry, the effect of the thermal noise results in a 1/f region in the output noise spectrum, while the flicker noise in a 1/f PLL input and supposing that the VCO is dominated by its 1/f 198/231 is the maximum time period of the PLL output clock and T ST10F276E and T , max min ...

Page 199

... Its effect is strongly reduced thanks to particular care used in the physical implementation and integration of the PLL module inside the device. In any case, the contribution of digital noise to global jitter is widely taken into account in the curves provided in Figure Figure 53. ST10F276E PLL jitter ±5 ±4 ±3 ±2 ± ...

Page 200

... A Parameter Conditions (1) Peak to peak (1) Sine wave middle Stable V DD (1) Stable This feature allows to recover from a Value Min. Max -500 +500 250 2000 500 4000 Value Min. Typ 0 -0. crystal - 3 , resonator - 2 ST10F276E Unit 300 µs 250 ps kHz Unit Max ...