ST10F273M-4TR3 STMicroelectronics, ST10F273M-4TR3 Datasheet - Page 134

• Manufacturer Part Number: ST10F273M-4TR3
• Description: MCU 16BIT 512K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F273M-4TR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical characteristics
1. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float
2. Port 5 leakage values are granted for not selected A/D converter channel. One channels is always selected (by default,
3.
4. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used
5. The maximum current may be drawn while the respective signal line remains inactive.
6. The minimum current must be drawn in order to drive the respective signal line active.
7. The power supply current is a function of the operating frequency (f
8. Not 100% tested, guaranteed by design characterization.
9. The power supply current is a function of the operating frequency (f
10. The Idle mode supply current is a function of the operating frequency (f
11. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at V
12. Overload conditions occur if the standard operating conditions are exceeded, that is, the voltage on any pin exceeds the
13. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at V
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and the voltage is imposed by the external circuitry.
after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.
Consult your vendor to know which version of the on-chip oscillator amplifier is enabled (Low-Power or Wide-Swing).
The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)
implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:
failures in Flash reading may occur (sense amplifier perturbation). Refer to next
circuitry.
for CS output and the open drain function is not enabled.
illustrated in the Figure
outputs disconnected and all inputs at V
The device is doing the following:
Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules
Watchdog Timer is enabled and regularly serviced
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channels of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
illustrated in the
disconnected and all inputs at V
device is doing the following:
Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM
Watchdog Timer is enabled and regularly serviced
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channels of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
illustrated in the
and all inputs at V
– 0.1 V to V
Regulator is assumed off: in case it is not, additional 1mA shall be assumed. The value for this parameter shall be
considered as “Target Value” to be confirmed by silicon characterization.
specified range (that is, V
may not exceed 50mA. The supply voltage must remain within the specified limits.
– 0.1 V to V
Regulator is assumed off: in case it is not, additional 1mA shall be assumed. The value for this parameter shall be
considered as “Target Value” to be confirmed by silicon characterization.
DD
DD
, V
, V
Figure 39
Figure 38
AREF
AREF
IL
or V
= 0 V, all outputs (including pins configured as outputs) disconnected. Besides, the Main Voltage
= 0 V, all outputs (including pins configured as outputs) disconnected. Besides, the Main Voltage
Figure 39
IH
OV
, RSTIN pin at V
below. This parameter is tested at V
below. These parameters are tested and at maximum CPU clock with all outputs disconnected
> V
IL
DD
below. This parameter is tested at V
or V
+ 0.3 V or V
IH
IL
, RSTIN pin at V
or V
IH1Min.
IH
OV
, RSTIN pin at V
< –0.3 V). The absolute sum of input overload currents on all port pins
IH1min
DDmax
: This implies that I/O current is not considered. The
IH1min
CPU
CPU
and at maximum CPU clock frequency with all outputs
DDmax
: This implies that I/O current is not considered.
CPU
is expressed in MHz). This dependency is
is expressed in MHz). This dependency is
is expressed in MHz). This dependency is
and at maximum CPU clock frequency with all
Figure 38
for a scheme of the input
ST10F273M
DD
DD