ST10F276Z5Q3TR STMicroelectronics, ST10F276Z5Q3TR Datasheet - Page 228

• Manufacturer Part Number: ST10F276Z5Q3TR
• Description: MCU 16BIT 832KBIT FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5Q3TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Interface Type: CAN, I2C
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Known limitations
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24.1
24.1.1
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Known limitations
This section describes the functional and electrical limitations identified on the CEG silicon
revision of the ST10F276Z5.
The major revision of the device is contained in the device identification register, IDCHIP,
located at address F07Ch. For Cxx versions, IDCHIP is set to 1143h.
Functional limitations
The function limitations identified on the ST10F276Z5 are the following:
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Injected conversion stalling the A/D converter
Description
The A/D converter is stalled and no further conversions are performed when a new injection
request is issued before the CPU reads the ADDAT2 register (that is when the CPU has not
read the result of the previous injection request).
Workarounds and recovery actions
The following actions allow to unlock the A/D converter:
1.
2.
Application conditions
This problem occurs if all the following conditions are fulfilled:
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Injected conversion stalling the A/D converter (see
stalling the A/D
Concurrent transmission requests in DAR mode (C-CAN module) (see
Concurrent transmission requests in DAR-mode (C-CAN
Disabling transmission requests (see
requests (C-CAN
Spurious BREQ pulse in slave mode during external bus arbitration phase (see
Section 24.1.4: Spurious BREQ pulse in slave mode during external bus arbitration
phase)
Executing PWRDN instructions (see
Behavior of capture/compare (CAPCOM) outputs in COMPARE mode 3 (see
Section 24.1.6: Behavior of CAPCOM outputs in COMPARE mode
Read the ADDAT2 register twice at the end of every injected conversion. This action
also prevents the ADC from being stalled.
Disable and then enable again the wait for read mode.
Injection requests are hardware triggered (via CapCom CC31).
The results of injected conversions are read by performing a PEC transfer. This
prevents from reading twice the ADDAT2 register by software.
A high level task is disabling the PEC transfer for a long time (time needed for 2 analog
conversions plus time between 2 injection requests).
converter)
module))
Section 24.1.5: Executing PWRDN
Section 24.1.3: Disabling the transmission
Section 24.1.1: Injected conversion
module))
3)
Section 24.1.2:
instructions)
ST10F276Z5