MC9S08QD2MSCR Freescale Semiconductor, MC9S08QD2MSCR Datasheet - Page 123

• Manufacturer Part Number: MC9S08QD2MSCR
• Description: IC MCU 8BIT 8-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QD2MSCR

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 16MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: S08QD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QD4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

9.1.2
Key features of the ICS module are:
9.1.3
There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop.
9.1.3.1
In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL
which is controlled by the internal reference clock. The BDC clock is supplied from the FLL.
9.1.3.2
In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is controlled by an
external reference clock. The BDC clock is supplied from the FLL.
9.1.3.3
In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is
bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied
from the FLL.
9.1.3.4
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock. The BDC clock is not available.
Freescale Semiconductor
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Frequency-locked loop (FLL) is trimmable for accuracy
— 0.2% resolution using internal 32 kHz reference
— 2% deviation over voltage and temperature using internal 32 kHz reference
Internal or external reference clocks up to 5 MHz can be used to control the FLL
— 3 bit select for reference divider is provided
Internal reference clock has 9 trim bits available
Internal or external reference clocks can be selected as the clock source for the MCU
Whichever clock is selected as the source can be divided down
— 2 bit select for clock divider is provided
Control signals for a low power oscillator as the external reference clock are provided
— HGO, RANGE, EREFS, ERCLKEN, EREFSTEN
FLL engaged internal mode is automatically selected out of reset
– Allowable dividers are: 1, 2, 4, 8
– BDC clock is provided as a constant divide by 2 of the DCO output
Features
Modes of Operation
FLL Engaged Interna
FLL Engaged External
FLL Bypassed Interna
FLL Bypassed Interna
MC9S08QD4 Series MCU Data Sheet, Rev. 6
l (FEI)
l (FBI)
l Low Power (FBILP)
(FEE)
Internal Clock Source (S08ICSV1)
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