C8051T634-GM Silicon Laboratories Inc, C8051T634-GM Datasheet - Page 10
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C8051T634-GM
Manufacturer Part Number
C8051T634-GM
Description
IC MCU 2KB 20PIN QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T63xr
Specifications of C8051T634-GM
Program Memory Type
OTP
Program Memory Size
2KB (2K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T630DK
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1464 - KIT DEV FOR C8051T630 FAMILY
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1462-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051T634-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
C8051T630/1/2/3/4/5
List of Tables
2. Ordering Information
3. Pin Definitions
4. QFN-20 Package Specifications
5. Electrical Characteristics
6. 12. CIP-51 Microcontroller
14. Special Function Registers
15. Interrupts
16. EPROM Memory
20. Port Input/Output
21. SMBus
10
Table 2.1. Product Selection Guide ......................................................................... 17
Table 3.1. Pin Definitions for the C8051T630/1/2/3/4/5 ........................................... 18
Table 4.1. QFN-20 Package Dimensions ................................................................ 21
Table 4.2. QFN-20 PCB Land Pattern Dimesions ................................................... 22
Table 5.1. Absolute Maximum Ratings .................................................................... 23
Table 5.2. Global Electrical Characteristics ............................................................. 24
Table 5.3. Port I/O DC Electrical Characteristics ..................................................... 25
Table 5.4. Reset Electrical Characteristics .............................................................. 26
Table 5.5. Internal Voltage Regulator Electrical Characteristics ............................. 26
Table 5.6. EPROM Electrical Characteristics .......................................................... 26
Table 5.7. Internal High-Frequency Oscillator Electrical Characteristics ................. 27
Table 5.8. Internal Low-Frequency Oscillator Electrical Characteristics ................. 27
Table 5.9. ADC0 Electrical Characteristics .............................................................. 28
Table 5.10. Temperature Sensor Electrical Characteristics .................................... 29
Table 5.11. Voltage Reference Electrical Characteristics ....................................... 29
Table 5.12. IDAC Electrical Characteristics ............................................................. 30
Table 5.13. Comparator Electrical Characteristics .................................................. 31
Table 12.1. CIP-51 Instruction Set Summary .......................................................... 65
Table 14.1. Special Function Register (SFR) Memory Map .................................... 76
Table 14.2. Special Function Registers ................................................................... 77
Table 15.1. Interrupt Summary ................................................................................ 82
Table 16.1. Security Byte Decoding ........................................................................ 90
Table 20.1. Port I/O Assignment for Analog Functions ......................................... 112
Table 20.2. Port I/O Assignment for Digital Functions ........................................... 112
Table 20.3. Port I/O Assignment for External Digital Event Capture Functions .... 113
Table 21.1. SMBus Clock Source Selection .......................................................... 131
Table 21.2. Minimum SDA Setup and Hold Times ................................................ 132
Table 21.3. Sources for Hardware Changes to SMB0CN ..................................... 136
Table 21.4. Hardware Address Recognition Examples (EHACK = 1) ................... 137
Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled
Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 0) ....................................................................................... 144
(EHACK = 1) ....................................................................................... 146
Rev. 1.0