MC9S08AC8MFJE Freescale Semiconductor, MC9S08AC8MFJE Datasheet - Page 97
![IC MCU 8BIT 8K FLASH 32-LQFP](/photos/12/33/123395/mc9s08ac8mfje_sml.jpg)
MC9S08AC8MFJE
Manufacturer Part Number
MC9S08AC8MFJE
Description
IC MCU 8BIT 8K FLASH 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AC8CFGE.pdf
(336 pages)
Specifications of MC9S08AC8MFJE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-LQFP
Processor Series
S08AC
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08AC8MFJE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1
1
6.7.7
Port D parallel I/O function is controlled by the registers listed below.
Freescale Semiconductor
PTDDD[3:0]
Bits 7 through 4 are reserved bits that must always be written to 0.
Bits 7 through 4 are reserved bits that must always be written to 0.
PTDD[3:0]
Reset
Reset
Field
Field
3:0
3:0
W
W
R
R
Port D I/O Registers (PTDD and PTDDD)
Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
R
R
0
0
7
7
R
R
0
0
6
6
Figure 6-26. Data Direction for Port D (PTDDD)
Table 6-17. PTDDD Register Field Descriptions
Table 6-16. PTDD Register Field Descriptions
Figure 6-25. Port D Data Register (PTDD)
MC9S08AC16 Series Data Sheet, Rev. 8
R
R
0
0
5
5
R
R
0
0
4
4
Description
Description
PTDDD3
PTDD3
3
0
3
0
PTDDD2
PTDD2
1
0
0
2
2
1
Chapter 6 Parallel Input/Output
PTDDD1
PTDD1
0
0
1
1
PTDDD0
PTDD0
0
0
0
0
97
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