MC9S08GT16ACFDER Freescale Semiconductor, MC9S08GT16ACFDER Datasheet - Page 202

• Manufacturer Part Number: MC9S08GT16ACFDER
• Description: IC MCU 8BIT 16K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT16ACFDER

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Package: 48QFN EP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 39
• Interface Type: I2C/SCI/SPI
• On-chip Adc: 8-chx10-bit
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Serial Peripheral Interface (S08SPIV3)
12.6.1.2
In this example, the SPI module will be set up for master mode with only transmit interrupts enabled to
run at a maximum baud rate of bus clock divided by 2. Clock phase and polarity will be set for an
active-high SPI clock where the first edge on SPSCK occurs at the start of the first cycle of a data transfer.
202
SPIC1 = 0x74(%01110100)
SPIC2 = 0x00(%00000000)
SPIBR = 0x00(%00000000)
SPIS = 0x00(%00000000)
SPID = 0xxx
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7:5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6:4
Bit 3
Bit 2:0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3:0
Holds data to be transmitted by transmit buffer and data received by receive buffer.
Pseudo—Code Example
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
MODFEN
BIDIROE
SPISWAI
SPC0
SPRF
SPTEF
MODF
= 0
= 1
= 1
= 1
= 0
= 1
= 0
= 0
= 000
= 0
= 0
= 0
= 0
= 0
= 0
= 000
= 0
= 000
= 0
= 0
= 0
= 0
= 0
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Disables receive and mode fault interrupts
Enables the SPI system
Enables SPI transmit interrupts
Sets the SPI module as a master SPI device
Configures SPI clock as active-high
First edge on SPSCK at start of first data transfer cycle
Determines SS pin function when mode fault enabled
SPI serial data transfers start with most significant bit
Unimplemented
Disables mode fault function
SPI data I/O pin acts as input
Unimplemented
SPI clocks operate in wait mode
SPI uses separate pins for data input and output
Unimplemented
Sets prescale divisor to 1
Unimplemented
Sets baud rate divisor to 2
Flag is set when receive data buffer is full
Unimplemented
Flag is set when transmit data buffer is empty
Mode fault flag for master mode
Unimplemented
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