MC9S08AC48CFDE Freescale Semiconductor, MC9S08AC48CFDE Datasheet - Page 152
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MC9S08AC48CFDE
Manufacturer Part Number
MC9S08AC48CFDE
Description
IC MCU 8BIT 48K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AC60CFJE.pdf
(348 pages)
Specifications of MC9S08AC48CFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08AC
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SCI, SPI
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08AC48CFDE
Manufacturer:
INTEL
Quantity:
210
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Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion
algorithm.
If the bus frequency is less than the f
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the f
sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
152
ADCK
Single or first continuous 10-bit
Single or first continuous 10-bit
Single or first continuous 10-bit
Single or first continuous 10-bit
Subsequent continuous 10-bit;
Subsequent continuous 10-bit;
Single or first continuous 8-bit
Single or first continuous 8-bit
Single or first continuous 8-bit
Single or first continuous 8-bit
Subsequent continuous 8-bit;
Subsequent continuous 8-bit;
frequency, precise sample time for continuous conversions cannot be guaranteed when long
Conversion Type
Conversion time =
f
f
BUS
BUS
The ADCK frequency must be between f
maximum to meet ADC specifications.
f
f
BUS
BUS
> f
> f
> f
> f
ADCK
ADCK
ADCK
ADCK
Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles
Table 9-11. Total Conversion Time vs. Control Conditions
/11
/11
MC9S08AC60 Series Data Sheet, Rev. 2
ADCK
23 ADCK cyc
8 MHz/1
frequency, precise sample time for continuous conversions
ADICLK
0x, 10
0x, 10
0x, 10
0x, 10
11
11
11
11
xx
xx
xx
xx
NOTE
ADLSMP
+
ADCK
0
0
1
1
0
0
1
1
0
0
1
1
5 bus cyc
minimum and f
8 MHz
20 ADCK cycles + 5 bus clock cycles
23 ADCK cycles + 5 bus clock cycles
40 ADCK cycles + 5 bus clock cycles
43 ADCK cycles + 5 bus clock cycles
5 μs + 20 ADCK + 5 bus clock cycles
5 μs + 23 ADCK + 5 bus clock cycles
5 μs + 40 ADCK + 5 bus clock cycles
5 μs + 43 ADCK + 5 bus clock cycles
Max Total Conversion Time
= 3.5 μs
ADCK
17 ADCK cycles
20 ADCK cycles
37 ADCK cycles
40 ADCK cycles
Table
Freescale Semiconductor
9-11.
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