MC9S08GT32ACFDER Freescale Semiconductor, MC9S08GT32ACFDER Datasheet - Page 217
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MC9S08GT32ACFDER
Manufacturer Part Number
MC9S08GT32ACFDER
Description
MCU 8BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08GT60ACFDER.pdf
(302 pages)
Specifications of MC9S08GT32ACFDER
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S08GT
Core
HCS08
3rd Party Development Tools
EWS08
Development Tools By Supplier
M68EVB908GB60E, M68DEMO908GB60E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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13.4.1.4
The master can terminate the communication by generating a STOP signal to free the bus. However, the
master may generate a START signal followed by a calling command without generating a STOP signal
first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while
SCL at logical 1 (see
The master can generate a STOP even if the slave has generated an acknowledge at which point the slave
must release the bus.
13.4.1.5
As shown in
a STOP signal to terminate the communication. This is used by the master to communicate with another
slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
13.4.1.6
The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or
more masters try to control the bus at the same time, a clock synchronization procedure determines the bus
clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest
one among the masters. The relative priority of the contending masters is determined by a data arbitration
procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The
losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case,
the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is
set by hardware to indicate loss of arbitration.
13.4.1.7
Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all
the devices connected on the bus. The devices start counting their low period and after a device’s clock has
gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to
high in this device clock may not change the state of the SCL line if another device clock is still within its
low period. Therefore, synchronized clock SCL is held low by the device with the longest low period.
Devices with shorter low periods enter a high wait state during this time (see
devices concerned have counted off their low period, the synchronized clock SCL line is released and
pulled high. There is then no difference between the device clocks and the state of the SCL line and all the
devices start counting their high periods. The first device to complete its high period pulls the SCL line
low again.
Freescale Semiconductor
Figure
STOP Signal
Repeated START Signal
Arbitration Procedure
Clock Synchronization
13-8, a repeated START signal is a START signal generated without first generating
Figure
13-8).
MC9S08GB60A Data Sheet, Rev. 2
Figure
Inter-Integrated Circuit (S08IICV1)
13-9). When all
217
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