MC9S08GT32ACFDER Freescale Semiconductor, MC9S08GT32ACFDER Datasheet - Page 220
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MC9S08GT32ACFDER
Manufacturer Part Number
MC9S08GT32ACFDER
Description
MCU 8BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08GT60ACFDER.pdf
(302 pages)
Specifications of MC9S08GT32ACFDER
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S08GT
Core
HCS08
3rd Party Development Tools
EWS08
Development Tools By Supplier
M68EVB908GB60E, M68DEMO908GB60E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Inter-Integrated Circuit (S08IICV1)
13.7
220
1.
2.
3.
4.
1.
2.
3.
4.
5.
6.
7.
Write: IICA
— to set the slave address
Write: IICC
— to enable IIC and interrupts
Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
Initialize RAM variables used to achieve the routine shown in
Write: IICF
— to set the IIC baud rate (example provided in this chapter)
Write: IICC
— to enable IIC and interrupts
Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
Initialize RAM variables used to achieve the routine shown in
Write: IICC
— to enable TX
Write: IICC
— to enable MST (master mode)
Write: IICD
— with the address of the target slave. (The LSB of this byte will determine whether the communication is
The routine shown in
incoming IIC message that contains the proper address will begin IIC communication. For master operation,
communication must be initiated by writing to the IICD register.
Initialization/Application Information
IICC
IICD
IICA
IICS
IICF
master receive or transmit.)
Address to which the module will respond when addressed as a slave (in slave mode)
Data register; Write to transmit IIC data read to read IIC data
Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER))
Module configuration
Module status flags
IICEN
TCF
MULT
Figure 13-11
IICIE
IAAS
Figure 13-10. IIC Module Quick Start
BUSY
MST
Module Initialization (Master)
MC9S08GB60A Data Sheet, Rev. 2
Module Initialization (Slave)
can handle both master and slave IIC operations. For slave operation, an
Register Model
ARBL
Module Use
TX
ADDR
DATA
TXAK
0
ICR
Figure 13-11
Figure 13-11
RSTA
SRW
IICIF
0
RXAK
0
0
Freescale Semiconductor
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