MC9S08GT32ACFDER Freescale Semiconductor, MC9S08GT32ACFDER Datasheet - Page 68
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MC9S08GT32ACFDER
Manufacturer Part Number
MC9S08GT32ACFDER
Description
MCU 8BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08GT60ACFDER.pdf
(302 pages)
Specifications of MC9S08GT32ACFDER
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S08GT
Core
HCS08
3rd Party Development Tools
EWS08
Development Tools By Supplier
M68EVB908GB60E, M68DEMO908GB60E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Chapter 5 Resets, Interrupts, and System Configuration
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part
of the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address just recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR.
Typically, the flag should be cleared at the beginning of the ISR so that if another interrupt is generated by
this same source, it will be registered so it can be serviced after completion of the current ISR.
5.5.2
External interrupts are managed by the IRQSC status and control register. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.
5.5.2.1
The IRQ pin enable (IRQPE) control bit in the IRQSC register must be 1 for the IRQ pin to act as the
interrupt request (IRQ) input. When the pin is configured as an IRQ input, the user can choose the polarity
of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD),
and whether an event causes an interrupt or only sets the IRQF flag (which can be polled by software).
When the IRQ pin is configured to detect rising edges, an optional pulldown resistor is available rather
than a pullup resistor. BIH and BIL instructions may be used to detect the level on the IRQ pin when the
pin is configured to act as the IRQ input.
68
External Interrupt Request (IRQ) Pin
Pin Configuration Options
The voltage measured on the pulled up IRQ pin may be as low as V
V. The internal gates connected to this pin are pulled all the way to V
other pins with enabled pullup resistors will have an unloaded measurement
of V
DD
.
STACKING
ORDER
UNSTACKING
5
4
3
2
1
ORDER
1
2
3
4
5
* High byte (H) of index register is not automatically stacked.
7
INDEX REGISTER (LOW BYTE X)
Figure 5-1. Interrupt Stack Frame
CONDITION CODE REGISTER
MC9S08GB60A Data Sheet, Rev. 2
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
ACCUMULATOR
²
²
²
²
NOTE
TOWARD HIGHER ADDRESSES
TOWARD LOWER ADDRESSES
*
0
SP AFTER
INTERRUPT STACKING
SP BEFORE
THE INTERRUPT
DD
DD
Freescale Semiconductor
– 0.7
. All
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