C8051F338-GMR Silicon Laboratories Inc, C8051F338-GMR Datasheet - Page 132
C8051F338-GMR
Manufacturer Part Number
C8051F338-GMR
Description
IC MCU 16K FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F338-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
24-QFN
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
21
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F336DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
10 bit
Height
0.73 mm
Length
4 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
Q4962654
T1084322
T1084322
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C8051F336/7/8/9
SFR Definition 20.7. P0: Port 0
SFR Address = 0x80; Bit Addressable
SFR Definition 20.8. P0MDIN: Port 0 Input Mode
SFR Address = 0xF1
132
Name
Reset
Name
Reset
7:0
7:0
Bit
Bit
Type
Type
Bit
Bit
P0MDIN[7:0]
P0[7:0]
Name
Name
7
1
7
1
Port 0 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
6
1
6
1
Description
5
1
5
1
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
Rev.1.0
4
1
4
1
P0MDIN[7:0]
P0[7:0]
R/W
R/W
Function
Write
3
1
3
1
2
1
2
1
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
1
1
1
1
Read
0
1
0
1
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